irqchip: dw-apb-ictl: ipipe: enable pipelined interrupts

diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
index 0a19618ce2c8bc89e52264b9122072281c8bdeb4..061189b56fd589005e33db54accb6b4a690808de 100644 (file)
--- a/drivers/irqchip/irq-dw-apb-ictl.c
+++ b/drivers/irqchip/irq-dw-apb-ictl.c
@@ -17,6 +17,7 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/ipipe.h>
 
 #define APB_INT_ENABLE_L       0x00
 #define APB_INT_ENABLE_H       0x04
@@ -42,7 +43,7 @@ static void dw_apb_ictl_handler(struct irq_desc *desc)
                        u32 hwirq = ffs(stat) - 1;
                        u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
 
-                       generic_handle_irq(virq);
+                       ipipe_handle_demuxed_irq(virq);
                        stat &= ~(1 << hwirq);
                }
        }
@@ -55,11 +56,12 @@ static void dw_apb_ictl_resume(struct irq_data *d)
 {
        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+       unsigned long flags;
 
-       irq_gc_lock(gc);
+       flags = irq_gc_lock(gc);
        writel_relaxed(~0, gc->reg_base + ct->regs.enable);
        writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);
-       irq_gc_unlock(gc);
+       irq_gc_unlock(gc, flags);
 }
 #else
 #define dw_apb_ictl_resume     NULL
@@ -144,6 +146,7 @@ static int __init dw_apb_ictl_init(struct device_node *np,
                gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
                gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
                gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
+               gc->chip_types[0].chip.flags |= IRQCHIP_PIPELINE_SAFE;
        }
 
        irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain);