* arm/predicates.md (zero_operand, reg_or_zero_operand): New predicates.

* arm/neon.md (neon_vceq<mode>, neon_vcge<mode>): Use
reg_or_zero_operand predicate.
(neon_vcle<mode>, neon_vclt<mode>): Use zero_operand predicate.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@185573 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d2dcbe5..0269a51 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2012-03-20  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm/predicates.md (zero_operand, reg_or_zero_operand): New predicates.
+       * arm/neon.md (neon_vceq<mode>, neon_vcge<mode>): Use
+       reg_or_zero_operand predicate.
+       (neon_vcle<mode>, neon_vclt<mode>): Use zero_operand predicate.
+
 2012-03-20  Jakub Jelinek  <jakub@redhat.com>
 
        * config/i386/i386.c (ix86_decompose_address) <case ZERO_EXTEND>:

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 078a8fd..44dee53 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2114,7 +2114,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
         (unspec:<V_cmp_result>
          [(match_operand:VDQW 1 "s_register_operand" "w,w")
-          (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
+          (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
           (match_operand:SI 3 "immediate_operand" "i,i")]
           UNSPEC_VCEQ))]
   "TARGET_NEON"
@@ -2133,7 +2133,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
         (unspec:<V_cmp_result>
          [(match_operand:VDQW 1 "s_register_operand" "w,w")
-          (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
+          (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
           (match_operand:SI 3 "immediate_operand" "i,i")]
           UNSPEC_VCGE))]
   "TARGET_NEON"
@@ -2164,7 +2164,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w")
         (unspec:<V_cmp_result>
          [(match_operand:VDQW 1 "s_register_operand" "w,w")
-          (match_operand:VDQW 2 "nonmemory_operand" "w,Dz")
+          (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")
            (match_operand:SI 3 "immediate_operand" "i,i")]
           UNSPEC_VCGT))]
   "TARGET_NEON"
@@ -2198,7 +2198,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
         (unspec:<V_cmp_result>
          [(match_operand:VDQW 1 "s_register_operand" "w")
-          (match_operand:VDQW 2 "nonmemory_operand" "Dz")
+          (match_operand:VDQW 2 "zero_operand" "Dz")
           (match_operand:SI 3 "immediate_operand" "i")]
           UNSPEC_VCLE))]
   "TARGET_NEON"
@@ -2215,7 +2215,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
         (unspec:<V_cmp_result>
          [(match_operand:VDQW 1 "s_register_operand" "w")
-          (match_operand:VDQW 2 "nonmemory_operand" "Dz")
+          (match_operand:VDQW 2 "zero_operand" "Dz")
           (match_operand:SI 3 "immediate_operand" "i")]
           UNSPEC_VCLT))]
   "TARGET_NEON"

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index dea3a96..9171d73 100644 (file)
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -89,6 +89,15 @@
                  && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
 })
 
+(define_predicate "zero_operand"
+  (and (match_code "const_int,const_double,const_vector")
+       (match_test "op == CONST0_RTX (mode)")))
+
+;; Match a register, or zero in the appropriate mode.
+(define_predicate "reg_or_zero_operand"
+  (ior (match_operand 0 "s_register_operand")
+       (match_operand 0 "zero_operand")))
+
 (define_special_predicate "subreg_lowpart_operator"
   (and (match_code "subreg")
        (match_test "subreg_lowpart_p (op)")))