(define_register_constraint "Z7" "NOT_SP_REGS"
"@internal")
+(define_constraint "Za" "@internal" (match_test "pre_incdec_with_reg (op, 0)"))
+(define_constraint "Zb" "@internal" (match_test "pre_incdec_with_reg (op, 1)"))
+(define_constraint "Zc" "@internal" (match_test "pre_incdec_with_reg (op, 2)"))
+(define_constraint "Zd" "@internal" (match_test "pre_incdec_with_reg (op, 3)"))
+(define_constraint "Ze" "@internal" (match_test "pre_incdec_with_reg (op, 4)"))
+(define_constraint "Zf" "@internal" (match_test "pre_incdec_with_reg (op, 5)"))
+(define_constraint "Zg" "@internal" (match_test "pre_incdec_with_reg (op, 6)"))
+(define_constraint "Zh" "@internal" (match_test "pre_incdec_with_reg (op, 7)"))
extern int h8300_regs_ok_for_stm (int, rtx[]);
extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int);
extern bool h8300_move_ok (rtx, rtx);
+extern bool pre_incdec_with_reg (rtx, int);
struct cpp_reader;
extern void h8300_pr_interrupt (struct cpp_reader *);
return 1;
}
+
+/* Return TRUE if OP is a PRE_INC or PRE_DEC
+ instruction using REG, FALSE otherwise. */
+
+bool
+pre_incdec_with_reg (rtx op, int reg)
+{
+ /* OP must be a MEM. */
+ if (GET_CODE (op) != MEM)
+ return false;
+
+ /* The address must be a PRE_INC or PRE_DEC. */
+ op = XEXP (op, 0);
+ if (GET_CODE (op) != PRE_DEC && GET_CODE (op) != PRE_INC)
+ return false;
+
+ /* It must be a register that is being incremented
+ or decremented. */
+ op = XEXP (op, 0);
+ if (!REG_P (op))
+ return false;
+
+ /* Finally, check that the register number matches. */
+ return REGNO (op) == reg;
+}
+
\f
/* Initialize the GCC target structure. */
#undef TARGET_ATTRIBUTE_TABLE