clk: meson: mpll: add init callback and regs

Until now (gx and axg), the mpll setting on boot (whatever the
bootloader) was good enough to generate a clean fractional division.

It is not the case on the g12a. While moving away from the vendor u-boot,
it was noticed the fractional part of the divider was no longer applied.
Like on the pll, some magic settings need to applied on the mpll
register.

This change adds the ability to do that on the mpll driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index d3f42e0..2d39a8b 100644 (file)
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -115,8 +115,30 @@ static int mpll_set_rate(struct clk_hw *hw,
        else
                __acquire(mpll->lock);
 
-       /* Enable and set the fractional part */
+       /* Set the fractional part */
        meson_parm_write(clk->map, &mpll->sdm, sdm);
+
+       /* Set the integer divider part */
+       meson_parm_write(clk->map, &mpll->n2, n2);
+
+       if (mpll->lock)
+               spin_unlock_irqrestore(mpll->lock, flags);
+       else
+               __release(mpll->lock);
+
+       return 0;
+}
+
+static void mpll_init(struct clk_hw *hw)
+{
+       struct clk_regmap *clk = to_clk_regmap(hw);
+       struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
+
+       if (mpll->init_count)
+               regmap_multi_reg_write(clk->map, mpll->init_regs,
+                                      mpll->init_count);
+
+       /* Enable the fractional part */
        meson_parm_write(clk->map, &mpll->sdm_en, 1);
 
        /* Set spread spectrum if possible */
@@ -126,19 +148,9 @@ static int mpll_set_rate(struct clk_hw *hw,
                meson_parm_write(clk->map, &mpll->ssen, ss);
        }
 
-       /* Set the integer divider part */
-       meson_parm_write(clk->map, &mpll->n2, n2);
-
        /* Set the magic misc bit if required */
        if (MESON_PARM_APPLICABLE(&mpll->misc))
                meson_parm_write(clk->map, &mpll->misc, 1);
-
-       if (mpll->lock)
-               spin_unlock_irqrestore(mpll->lock, flags);
-       else
-               __release(mpll->lock);
-
-       return 0;
 }
 
 const struct clk_ops meson_clk_mpll_ro_ops = {
@@ -151,6 +163,7 @@ const struct clk_ops meson_clk_mpll_ops = {
        .recalc_rate    = mpll_recalc_rate,
        .round_rate     = mpll_round_rate,
        .set_rate       = mpll_set_rate,
+       .init           = mpll_init,
 };
 EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
 

diff --git a/drivers/clk/meson/clk-mpll.h b/drivers/clk/meson/clk-mpll.h
index 0f94843..a991d56 100644 (file)
--- a/drivers/clk/meson/clk-mpll.h
+++ b/drivers/clk/meson/clk-mpll.h
@@ -18,6 +18,8 @@ struct meson_clk_mpll_data {
        struct parm n2;
        struct parm ssen;
        struct parm misc;
+       const struct reg_sequence *init_regs;
+       unsigned int init_count;
        spinlock_t *lock;
        u8 flags;
 };