radv: Add sbt descriptors user SGPR input.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tue, 23 Mar 2021 01:20:55 +0000 (02:20 +0100)
committerMarge Bot <eric+marge@anholt.net>
Tue, 18 May 2021 18:29:36 +0000 (18:29 +0000)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>

src/amd/common/ac_shader_args.h
src/amd/vulkan/radv_shader.h
src/amd/vulkan/radv_shader_args.c
src/amd/vulkan/radv_shader_info.c

index 2cbc116..4da9d06 100644 (file)
@@ -142,6 +142,7 @@ struct ac_shader_args {
    unsigned num_inline_push_consts;
    unsigned base_inline_push_consts;
    struct ac_arg view_index;
+   struct ac_arg sbt_descriptors;
 };
 
 void ac_add_arg(struct ac_shader_args *info, enum ac_arg_regfile regfile, unsigned registers,
index c6097b8..86aa86e 100644 (file)
@@ -167,6 +167,7 @@ enum radv_ud_index {
    AC_UD_VS_MAX_UD,
    AC_UD_PS_MAX_UD,
    AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
+   AC_UD_CS_SBT_DESCRIPTORS,
    AC_UD_CS_MAX_UD,
    AC_UD_GS_MAX_UD,
    AC_UD_TCS_MAX_UD,
@@ -335,6 +336,8 @@ struct radv_shader_info {
       bool uses_thread_id[3];
       bool uses_local_invocation_idx;
       unsigned block_size[3];
+
+      bool uses_sbt;
    } cs;
    struct {
       uint64_t tes_inputs_read;
index 173f6bc..d0fde54 100644 (file)
@@ -173,6 +173,8 @@ allocate_user_sgprs(struct radv_shader_args *args, gl_shader_stage stage, bool h
 
    switch (stage) {
    case MESA_SHADER_COMPUTE:
+      if (args->shader_info->cs.uses_sbt)
+         user_sgpr_count += 1;
       if (args->shader_info->cs.uses_grid_size)
          user_sgpr_count += 3;
       break;
@@ -442,6 +444,10 @@ radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
    case MESA_SHADER_COMPUTE:
       declare_global_input_sgprs(args, &user_sgpr_info);
 
+      if (args->shader_info->cs.uses_sbt) {
+         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &args->ac.sbt_descriptors);
+      }
+
       if (args->shader_info->cs.uses_grid_size) {
          ac_add_arg(&args->ac, AC_ARG_SGPR, 3, AC_ARG_INT, &args->ac.num_work_groups);
       }
@@ -652,6 +658,9 @@ radv_declare_shader_args(struct radv_shader_args *args, gl_shader_stage stage,
 
    switch (stage) {
    case MESA_SHADER_COMPUTE:
+      if (args->shader_info->cs.uses_sbt) {
+         set_loc_shader_ptr(args, AC_UD_CS_SBT_DESCRIPTORS, &user_sgpr_idx);
+      }
       if (args->shader_info->cs.uses_grid_size) {
          set_loc_shader(args, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, 3);
       }
index 81f7ba4..f85173c 100644 (file)
@@ -266,6 +266,9 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
    case nir_intrinsic_store_output:
       gather_intrinsic_store_output_info(nir, instr, info);
       break;
+   case nir_intrinsic_load_sbt_amd:
+      info->cs.uses_sbt = true;
+      break;
    default:
       break;
    }