ARM: dts: stm32: Add ipcc mailbox support on stm32mp1

Add IPCC mailbox support on stm32mp157 eval and disco boards.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index e36773d..b8dd4ba 100644 (file)
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -228,6 +228,10 @@
        };
 };
 
+&ipcc {
+       status = "okay";
+};
+
 &iwdg2 {
        timeout-sec = <32>;
        status = "okay";

diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index b10208f..ab11c83 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -318,6 +318,10 @@
        };
 };
 
+&ipcc {
+       status = "okay";
+};
+
 &iwdg2 {
        timeout-sec = <32>;
        status = "okay";

diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 7321585..b9f0eac 100644 (file)
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -849,6 +849,19 @@
                        status = "disabled";
                };
 
+               ipcc: mailbox@4c001000 {
+                       compatible = "st,stm32mp1-ipcc";
+                       #mbox-cells = <1>;
+                       reg = <0x4c001000 0x400>;
+                       st,proc-id = <0>;
+                       interrupts-extended =
+                               <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                               <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "rx", "tx";
+                       clocks = <&rcc IPCC>;
+                       status = "disabled";
+               };
+
                rcc: rcc@50000000 {
                        compatible = "st,stm32mp1-rcc", "syscon";
                        reg = <0x50000000 0x1000>;