media: sun4i-csi: Fix [HV]sync polarity handling

The Allwinner camera sensor interface has a different definition of
[HV]sync. While the timing diagram uses the names HSYNC and VSYNC,
the note following the diagram and register names use HREF and VREF.
Combined they imply the hardware uses either [HV]REF or inverted
[HV]SYNC. There are also registers to set horizontal skip lengths
in pixels and vertical skip lengths in lines, also known as back
porches.

Fix the polarity handling by using the opposite polarity flag for
the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better
match the hardware register description.

Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
index 001c8bd..88d39b3 100644 (file)
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
@@ -22,8 +22,8 @@
 #define CSI_CFG_INPUT_FMT(fmt)                 ((fmt) << 20)
 #define CSI_CFG_OUTPUT_FMT(fmt)                        ((fmt) << 16)
 #define CSI_CFG_YUV_DATA_SEQ(seq)              ((seq) << 8)
-#define CSI_CFG_VSYNC_POL(pol)                 ((pol) << 2)
-#define CSI_CFG_HSYNC_POL(pol)                 ((pol) << 1)
+#define CSI_CFG_VREF_POL(pol)                  ((pol) << 2)
+#define CSI_CFG_HREF_POL(pol)                  ((pol) << 1)
 #define CSI_CFG_PCLK_POL(pol)                  ((pol) << 0)
 
 #define CSI_CPT_CTRL_REG               0x08

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
index 8b567d0..78fa1c5 100644 (file)
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
@@ -228,7 +228,7 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
        struct sun4i_csi *csi = vb2_get_drv_priv(vq);
        struct v4l2_fwnode_bus_parallel *bus = &csi->bus;
        const struct sun4i_csi_format *csi_fmt;
-       unsigned long hsync_pol, pclk_pol, vsync_pol;
+       unsigned long href_pol, pclk_pol, vref_pol;
        unsigned long flags;
        unsigned int i;
        int ret;
@@ -278,13 +278,21 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
        writel(CSI_WIN_CTRL_H_ACTIVE(csi->fmt.height),
               csi->regs + CSI_WIN_CTRL_H_REG);
 
-       hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
-       vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
+       /*
+        * This hardware uses [HV]REF instead of [HV]SYNC. Based on the
+        * provided timing diagrams in the manual, positive polarity
+        * equals active high [HV]REF.
+        *
+        * When the back porch is 0, [HV]REF is more or less equivalent
+        * to [HV]SYNC inverted.
+        */
+       href_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
+       vref_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
        pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);
        writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
               CSI_CFG_OUTPUT_FMT(csi_fmt->output) |
-              CSI_CFG_VSYNC_POL(vsync_pol) |
-              CSI_CFG_HSYNC_POL(hsync_pol) |
+              CSI_CFG_VREF_POL(vref_pol) |
+              CSI_CFG_HREF_POL(href_pol) |
               CSI_CFG_PCLK_POL(pclk_pol),
               csi->regs + CSI_CFG_REG);