drm/bridge: tc358768: Fix bit updates

[ Upstream commit 66962d5c3c51377b9b90cae35b7e038950438e02 ]

The driver has a few places where it does:

if (thing_is_enabled_in_config)
	update_thing_bit_in_hw()

This means that if the thing is _not_ enabled, the bit never gets
cleared. This affects the h/vsyncs and continuous DSI clock bits.

Fix the driver to always update the bit.

Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> # Asus TF700T
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230906-tc358768-v4-4-31725f008a50@ideasonboard.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c
index 16aa849..bdeda70 100644 (file)
--- a/drivers/gpu/drm/bridge/tc358768.c
+++ b/drivers/gpu/drm/bridge/tc358768.c
@@ -797,8 +797,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
                val |= BIT(i + 1);
        tc358768_write(priv, TC358768_HSTXVREGEN, val);
 
-       if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
-               tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
+       tc358768_write(priv, TC358768_TXOPTIONCNTRL,
+                      (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
 
        /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
        val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
@@ -864,11 +864,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
        tc358768_write(priv, TC358768_DSI_HACT, hact);
 
        /* VSYNC polarity */
-       if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
-               tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
+       tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
+                            (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
+
        /* HSYNC polarity */
-       if (mode->flags & DRM_MODE_FLAG_PHSYNC)
-               tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
+       tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
+                            (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
 
        /* Start DSI Tx */
        tc358768_write(priv, TC358768_DSI_START, 0x1);