Merge tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI update from Bjorn Helgaas:
 "Host bridge hotplug:
   - Untangle _PRT from struct pci_bus (Bjorn Helgaas)
   - Request _OSC control before scanning root bus (Taku Izumi)
   - Assign resources when adding host bridge (Yinghai Lu)
   - Remove root bus when removing host bridge (Yinghai Lu)
   - Remove _PRT during hot remove (Yinghai Lu)

  SRIOV
    - Add sysfs knobs to control numVFs (Don Dutile)

  Power management
   - Notify devices when power resource turned on (Huang Ying)

  Bug fixes
   - Work around broken _SEG on HP xw9300 (Bjorn Helgaas)
   - Keep runtime PM enabled for unbound PCI devices (Huang Ying)
   - Fix Optimus dual-GPU runtime D3 suspend issue (Dave Airlie)
   - Fix xen frontend shutdown issue (David Vrabel)
   - Work around PLX PCI 9050 BAR alignment erratum (Ian Abbott)

  Miscellaneous
   - Add GPL license for drivers/pci/ioapic (Andrew Cooks)
   - Add standard PCI-X, PCIe ASPM register #defines (Bjorn Helgaas)
   - NumaChip remote PCI support (Daniel Blueman)
   - Fix PCIe Link Capabilities Supported Link Speed definition (Jingoo
     Han)
   - Convert dev_printk() to dev_info(), etc (Joe Perches)
   - Add support for non PCI BAR ROM data (Matthew Garrett)
   - Add x86 support for host bridge translation offset (Mike Yoknis)
   - Report success only when every driver supports AER (Vijay
     Pandarathil)"

Fix up trivial conflicts.

* tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits)
  PCI: Use phys_addr_t for physical ROM address
  x86/PCI: Add NumaChip remote PCI support
  ath9k: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: collapse wrapper for pcie_capability_read_word()
  iwlegacy: Use standard #defines for PCIe Capability ASPM fields
  iwlegacy: collapse wrapper for pcie_capability_read_word()
  cxgb3: Use standard #defines for PCIe Capability ASPM fields
  PCI: Add standard PCIe Capability Link ASPM field names
  PCI/portdrv: Use PCI Express Capability accessors
  PCI: Use standard PCIe Capability Link register field names
  x86: Use PCI setup data
  PCI: Add support for non-BAR ROMs
  PCI: Add pcibios_add_device
  EFI: Stash ROMs if they're not in the PCI BAR
  PCI: Add and use standard PCI-X Capability register names
  PCI/PM: Keep runtime PM enabled for unbound PCI devices
  xen-pcifront: Handle backend CLOSED without CLOSING
  PCI: SRIOV control and status via sysfs (documentation)
  PCI/AER: Report success only when every device has AER-aware driver
  ...

diff --cc arch/x86/Kconfig
Simple merge

diff --cc arch/x86/boot/compressed/eboot.c
Simple merge

diff --cc drivers/acpi/pci_irq.c
Simple merge

diff --cc drivers/acpi/pci_root.c
Simple merge

diff --cc drivers/net/wireless/ath/ath9k/pci.c
Simple merge

diff --cc drivers/net/wireless/iwlegacy/common.h
Simple merge

diff --cc drivers/net/wireless/iwlwifi/pcie/trans.c
index d66cad4,1dfa6be..35708b9
--- 1/drivers/net/wireless/iwlwifi/pcie/trans.c
--- 2/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@@ -94,10 -670,8 +94,8 @@@ static void iwl_pcie_set_pwr_vmain(stru
  
  /* PCI registers */
  #define PCI_CFG_RETRY_TIMEOUT 0x041
- #define PCI_CFG_LINK_CTRL_VAL_L0S_EN  0x01
- #define PCI_CFG_LINK_CTRL_VAL_L1_EN   0x02
  
 -static void iwl_apm_config(struct iwl_trans *trans)
 +static void iwl_pcie_apm_config(struct iwl_trans *trans)
  {
        struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
        u16 lctl;
@@@ -110,19 -684,20 +108,17 @@@
         * If not (unlikely), enable L0S, so there is at least some
         *    power savings, even without L1.
         */
 -
        pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
- 
-       if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
-                               PCI_CFG_LINK_CTRL_VAL_L1_EN) {
+       if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
                /* L1-ASPM enabled; disable(!) L0S */
                iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 -              dev_printk(KERN_INFO, trans->dev,
 -                         "L1 Enabled; Disabling L0S\n");
 +              dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
        } else {
                /* L1-ASPM disabled; enable(!) L0S */
                iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 -              dev_printk(KERN_INFO, trans->dev,
 -                         "L1 Disabled; Enabling L0S\n");
 +              dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
        }
-       trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
+       trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  }
  
  /*

diff --cc drivers/pci/ioapic.c
Simple merge

diff --cc drivers/pci/pci-driver.c
Simple merge

diff --cc drivers/pci/pci-sysfs.c
Simple merge

diff --cc drivers/pci/pci.c
Simple merge

diff --cc drivers/pci/pci.h
index e253881,11a713b..e851829
--- 1/drivers/pci/pci.h
--- 2/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@@ -158,7 -159,12 +158,8 @@@ static inline int pci_no_d1d2(struct pc
  }
  extern struct device_attribute pci_dev_attrs[];
  extern struct device_attribute pcibus_dev_attrs[];
 -#ifdef CONFIG_HOTPLUG
+ extern struct device_type pci_dev_type;
  extern struct bus_attribute pci_bus_attrs[];
 -#else
 -#define pci_bus_attrs NULL
 -#endif
  
  
  /**

diff --cc drivers/pci/probe.c
Simple merge

diff --cc drivers/pci/quirks.c
index 22ad3ee,0c59f7a..8f7a634
--- 1/drivers/pci/quirks.c
--- 2/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@@ -1790,7 -1790,46 +1790,46 @@@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_
                         PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
                         quirk_tc86c001_ide);
  
 -static void __devinit quirk_plx_pci9050(struct pci_dev *dev)
+ /*
+  * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
+  * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
+  * being read correctly if bit 7 of the base address is set.
+  * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
+  * Re-allocate the regions to a 256-byte boundary if necessary.
+  */
 -static void __devinit quirk_netmos(struct pci_dev *dev)
++static void quirk_plx_pci9050(struct pci_dev *dev)
+ {
+       unsigned int bar;
+ 
+       /* Fixed in revision 2 (PCI 9052). */
+       if (dev->revision >= 2)
+               return;
+       for (bar = 0; bar <= 1; bar++)
+               if (pci_resource_len(dev, bar) == 0x80 &&
+                   (pci_resource_start(dev, bar) & 0x80)) {
+                       struct resource *r = &dev->resource[bar];
+                       dev_info(&dev->dev,
+                                "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
+                                bar);
+                       r->start = 0;
+                       r->end = 0xff;
+               }
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                        quirk_plx_pci9050);
+ /*
+  * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
+  * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
+  * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
+  * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
+  *
+  * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
+  * driver.
+  */
+ DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
+ DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
+ 
 +static void quirk_netmos(struct pci_dev *dev)
  {
        unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
        unsigned int num_serial = dev->subsystem_device & 0xf;

diff --cc drivers/pci/xen-pcifront.c
Simple merge

diff --cc include/linux/efi.h
Simple merge

diff --cc include/linux/pci.h
Simple merge