drm/amd/display: Query GECC enable for SubVP disable

- We want to disable SubVP if Graphics Error Correction/Correcting Code
  (GECC) is enabled.
- After reading feature caps from DMCUB during init, use the GECC
  enable/disable info to determine if SubVP can be enabled or not.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e41107098ffe26f735aca0ecae3676dfdd2740bb..f52ab717ac7d75900a1ecc85b0db3248de7e9451 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -210,6 +210,7 @@ struct dc_dmub_caps {
        bool psr;
        bool mclk_sw;
        bool subvp_psr;
+       bool gecc_enable;
 };
 
 struct dc_caps {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 1e9ada8b131ce5ce7d0802642809549017b23c13..4950eaa4406b2bdb72d3d4d9e2f25f497ac0d2d9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -945,6 +945,7 @@ void dcn32_init_hw(struct dc *dc)
                dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
                dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
                dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
+               dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
                dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 9cc0e60890325668dc085b2d61d758064ee10268..a73cacef6e48dba99b8e888f79b9bbbe3ccc6cce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1141,7 +1141,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc,
         * 4. Display configuration passes validation
         * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
         */
-       if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
+       if (!dc->debug.force_disable_subvp && !dc->caps.dmub_caps.gecc_enable && dcn32_all_pipes_have_stream_and_plane(dc, context) &&
            !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) &&
                (*vlevel == context->bw_ctx.dml.soc.num_states ||
            vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||