gas/

2008-02-18  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.c (match_template): Disallow 'l' suffix when
	currently selected CPU has no 32-bit support.
	(parse_real_register): Do not return registers not available on
	currently selected CPU.

gas/testsuite/
2008-02-18  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/att-regs.s, gas/i386/att-regs.d,
	gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
	* gas/i386/i386.exp: Run new tests.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 56060ad..15bd417 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2008-02-18  Jan Beulich  <jbeulich@novell.com>
+
+       * config/tc-i386.c (match_template): Disallow 'l' suffix when
+       currently selected CPU has no 32-bit support.
+       (parse_real_register): Do not return registers not available on
+       currently selected CPU.
+
 2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/tc-i386.c (process_immext): Fix format.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 03360e3..80a1ac8 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3337,6 +3337,19 @@ match_template (void)
              || t->extension_opcode != 1 /* cmpxchg8b */))
        continue;
 
+      /* In general, don't allow 32-bit operands on pre-386.  */
+      else if (i.suffix == LONG_MNEM_SUFFIX
+              && !cpu_arch_flags.bitfield.cpui386
+              && (intel_syntax
+                  ? (!t->opcode_modifier.ignoresize
+                     && !intel_float_operand (t->name))
+                  : intel_float_operand (t->name) != 2)
+              && ((!operand_types[0].bitfield.regmmx
+                   && !operand_types[0].bitfield.regxmm)
+                  || (!operand_types[t->operands > 1].bitfield.regmmx
+                      && !!operand_types[t->operands > 1].bitfield.regxmm)))
+       continue;
+
       /* Do not verify operands when there are none.  */
       else
        {
@@ -7114,6 +7127,20 @@ parse_real_register (char *reg_string, char **end_op)
   if (operand_type_all_zero (&r->reg_type))
     return (const reg_entry *) NULL;
 
+  if ((r->reg_type.bitfield.reg32
+       || r->reg_type.bitfield.sreg3
+       || r->reg_type.bitfield.control
+       || r->reg_type.bitfield.debug
+       || r->reg_type.bitfield.test)
+      && !cpu_arch_flags.bitfield.cpui386)
+    return (const reg_entry *) NULL;
+
+  if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
+    return (const reg_entry *) NULL;
+
+  if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
+    return (const reg_entry *) NULL;
+
   /* Don't allow fake index register unless allow_index_reg isn't 0. */
   if (!allow_index_reg
       && (r->reg_num == RegEiz || r->reg_num == RegRiz))

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index eef8a7b..d973db7 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2008-02-18  Jan Beulich  <jbeulich@novell.com>
+
+       * gas/i386/att-regs.s, gas/i386/att-regs.d,
+       gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
+       * gas/i386/i386.exp: Run new tests.
+
 2008-02-14  Nick Clifton  <nickc@redhat.com>
 
        PR gas/5712

diff --git a/gas/testsuite/gas/i386/att-regs.d b/gas/testsuite/gas/i386/att-regs.d
new file mode 100644 (file)
index 0000000..6ab9d28
--- /dev/null
+++ b/gas/testsuite/gas/i386/att-regs.d
@@ -0,0 +1,45 @@
+#objdump: -drw
+#name: i386 AT&T register names
+
+.*: +file format .*i386.*
+
+Disassembly of section \.text:
+0+0 <.*>:
+.*[    ]+R_386_16[     ]+eax
+.*[    ]+R_386_16[     ]+rax
+.*[    ]+R_386_16[     ]+axl
+.*[    ]+R_386_16[     ]+r8b
+.*[    ]+R_386_16[     ]+r8w
+.*[    ]+R_386_16[     ]+r8d
+.*[    ]+R_386_16[     ]+r8
+.*[    ]+R_386_16[     ]+fs
+#.*[   ]+R_386_16[     ]+st
+.*[    ]+R_386_16[     ]+cr0
+.*[    ]+R_386_16[     ]+dr0
+.*[    ]+R_386_16[     ]+tr0
+.*[    ]+R_386_16[     ]+mm0
+.*[    ]+R_386_16[     ]+xmm0
+.*[    ]+R_386_32[     ]+rax
+.*[    ]+R_386_32[     ]+axl
+.*[    ]+R_386_32[     ]+r8b
+.*[    ]+R_386_32[     ]+r8w
+.*[    ]+R_386_32[     ]+r8d
+.*[    ]+R_386_32[     ]+r8
+#.*[   ]+R_386_32[     ]+st
+.*:[   ]+0f 20 c0[     ]+mov[  ]+%cr0,%eax
+.*:[   ]+0f 21 c0[     ]+mov[  ]+%db0,%eax
+.*:[   ]+0f 24 c0[     ]+mov[  ]+%tr0,%eax
+.*[    ]+R_386_32[     ]+mm0
+.*[    ]+R_386_32[     ]+xmm0
+.*:[   ]+dd c0[        ]+ffree[        ]+%st(\(0\))?
+.*:[   ]+0f ef c0[     ]+pxor[         ]+%mm0,%mm0
+.*:[   ]+0f 57 c0[     ]+xorps[        ]+%xmm0,%xmm0
+.*:[   ]+44[   ]+inc    %esp
+.*:[   ]+88 c0[        ]+mov[  ]+%al,%al
+.*:[   ]+66 44[        ]+inc[  ]+%sp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+.*:[   ]+44[   ]+inc    %esp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+.*:[   ]+4c[   ]+dec    %esp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+#pass

diff --git a/gas/testsuite/gas/i386/att-regs.s b/gas/testsuite/gas/i386/att-regs.s
new file mode 100644 (file)
index 0000000..b966509
--- /dev/null
+++ b/gas/testsuite/gas/i386/att-regs.s
@@ -0,0 +1,50 @@
+       .text
+       .att_syntax noprefix
+
+       .arch i286
+       .code16
+       mov     eax, ax                 ; add   al, (bx,si)
+       mov     rax, ax                 ; add   al, (bx,si)
+       mov     axl, ax                 ; add   al, (bx,si)
+       mov     r8b, ax                 ; add   al, (bx,si)
+       mov     r8w, ax                 ; add   al, (bx,si)
+       mov     r8d, ax                 ; add   al, (bx,si)
+       mov     r8, ax                  ; add   al, (bx,si)
+       mov     fs, ax                  ; add   al, (bx,si)
+#todo  mov     st, ax                  ; add   al, (bx,si)
+       mov     cr0, ax                 ; add   al, (bx,si)
+       mov     dr0, ax                 ; add   al, (bx,si)
+       mov     tr0, ax                 ; add   al, (bx,si)
+       mov     mm0, ax                 ; add   al, (bx,si)
+       mov     xmm0, ax                        ; add   al, (bx,si)
+
+       .arch generic32
+       .code32
+       mov     rax, eax
+       mov     axl, eax
+       mov     r8b, eax
+       mov     r8w, eax
+       mov     r8d, eax
+       mov     r8, eax
+#todo  mov     st, eax
+       mov     cr0, eax
+       mov     dr0, eax
+       mov     tr0, eax
+       mov     mm0, eax
+       mov     xmm0, eax
+
+#todo  .arch i387
+       ffree   st
+
+       .arch .mmx
+       pxor    mm0, mm0
+
+       .arch .sse
+       xorps   xmm0, xmm0
+
+       .arch generic64
+       .code64
+       mov     r8b, axl
+       mov     r8w, ax
+       mov     r8d, eax
+       mov     r8, rax

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9af66b8..442e235 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -146,6 +146,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
        run_dump_test "reloc32"
        run_list_test "reloc32" "--defsym _bad_=1"
        run_dump_test "mixed-mode-reloc32"
+       run_dump_test "att-regs"
+       run_dump_test "intel-regs"
     }
 
     # This is a PE specific test.

diff --git a/gas/testsuite/gas/i386/intel-regs.d b/gas/testsuite/gas/i386/intel-regs.d
new file mode 100644 (file)
index 0000000..cf52161
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel-regs.d
@@ -0,0 +1,45 @@
+#objdump: -drw
+#name: i386 Intel register names
+
+.*: +file format .*i386.*
+
+Disassembly of section \.text:
+0+0 <.*>:
+.*[    ]+R_386_16[     ]+eax
+.*[    ]+R_386_16[     ]+rax
+.*[    ]+R_386_16[     ]+axl
+.*[    ]+R_386_16[     ]+r8b
+.*[    ]+R_386_16[     ]+r8w
+.*[    ]+R_386_16[     ]+r8d
+.*[    ]+R_386_16[     ]+r8
+.*[    ]+R_386_16[     ]+fs
+#.*[   ]+R_386_16[     ]+st
+.*[    ]+R_386_16[     ]+cr0
+.*[    ]+R_386_16[     ]+dr0
+.*[    ]+R_386_16[     ]+tr0
+.*[    ]+R_386_16[     ]+mm0
+.*[    ]+R_386_16[     ]+xmm0
+.*[    ]+R_386_32[     ]+rax
+.*[    ]+R_386_32[     ]+axl
+.*[    ]+R_386_32[     ]+r8b
+.*[    ]+R_386_32[     ]+r8w
+.*[    ]+R_386_32[     ]+r8d
+.*[    ]+R_386_32[     ]+r8
+#.*[   ]+R_386_32[     ]+st
+.*:[   ]+0f 20 c0[     ]+mov[  ]+%cr0,%eax
+.*:[   ]+0f 21 c0[     ]+mov[  ]+%db0,%eax
+.*:[   ]+0f 24 c0[     ]+mov[  ]+%tr0,%eax
+.*[    ]+R_386_32[     ]+mm0
+.*[    ]+R_386_32[     ]+xmm0
+.*:[   ]+dd c0[        ]+ffree[        ]+%st(\(0\))?
+.*:[   ]+0f ef c0[     ]+pxor[         ]+%mm0,%mm0
+.*:[   ]+0f 57 c0[     ]+xorps[        ]+%xmm0,%xmm0
+.*:[   ]+44[   ]+inc    %esp
+.*:[   ]+88 c0[        ]+mov[  ]+%al,%al
+.*:[   ]+66 44[        ]+inc[  ]+%sp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+.*:[   ]+44[   ]+inc    %esp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+.*:[   ]+4c[   ]+dec    %esp
+.*:[   ]+89 c0[        ]+mov[  ]+%eax,%eax
+#pass

diff --git a/gas/testsuite/gas/i386/intel-regs.s b/gas/testsuite/gas/i386/intel-regs.s
new file mode 100644 (file)
index 0000000..df5baf2
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel-regs.s
@@ -0,0 +1,50 @@
+       .text
+       .intel_syntax noprefix
+
+       .arch i286
+       .code16
+       mov     ax, eax                 ; add   [bx+si], al
+       mov     ax, rax                 ; add   [bx+si], al
+       mov     ax, axl                 ; add   [bx+si], al
+       mov     ax, r8b                 ; add   [bx+si], al
+       mov     ax, r8w                 ; add   [bx+si], al
+       mov     ax, r8d                 ; add   [bx+si], al
+       mov     ax, r8                  ; add   [bx+si], al
+       mov     ax, fs                  ; add   [bx+si], al
+#todo  mov     ax, st                  ; add   [bx+si], al
+       mov     ax, cr0                 ; add   [bx+si], al
+       mov     ax, dr0                 ; add   [bx+si], al
+       mov     ax, tr0                 ; add   [bx+si], al
+       mov     ax, mm0                 ; add   [bx+si], al
+       mov     ax, xmm0                ; add   [bx+si], al
+
+       .arch generic32
+       .code32
+       mov     eax, rax
+       mov     eax, axl
+       mov     eax, r8b
+       mov     eax, r8w
+       mov     eax, r8d
+       mov     eax, r8
+#todo  mov     eax, st
+       mov     eax, cr0
+       mov     eax, dr0
+       mov     eax, tr0
+       mov     eax, mm0
+       mov     eax, xmm0
+
+#todo  .arch i387
+       ffree   st
+
+       .arch .mmx
+       pxor    mm0, mm0
+
+       .arch .sse
+       xorps   xmm0, xmm0
+
+       .arch generic64
+       .code64
+       mov     axl, r8b
+       mov     ax, r8w
+       mov     eax, r8d
+       mov     rax, r8