defm : BWWriteResPair<WriteCvtPD2IY, [BWPort1,BWPort5], 6, [1,1], 2, 6>;
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
-defm : BWWriteResPair<WriteCvtI2SS, [BWPort1], 4>;
+defm : X86WriteRes<WriteCvtI2SS, [BWPort1,BWPort5], 4, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2SSLd, [BWPort1,BWPort23], 9, [1,1], 2>;
defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 3>;
defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 3, [1], 1, 6>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
-defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>;
+defm : X86WriteRes<WriteCvtI2SD, [BWPort1,BWPort5], 4, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2SDLd, [BWPort1,BWPort23], 9, [1,1], 2>;
defm : BWWriteResPair<WriteCvtI2PD, [BWPort1,BWPort5], 4, [1,1], 2, 5>;
defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1,BWPort5], 6, [1,1], 2, 5>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
-defm : BWWriteResPair<WriteCvtSS2SD, [BWPort0,BWPort5], 2, [1,1], 2, 5>;
-defm : BWWriteResPair<WriteCvtPS2PD, [BWPort0,BWPort5], 2, [1,1], 2, 5>;
+defm : X86WriteRes<WriteCvtSS2SD, [BWPort0,BWPort5], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCvtSS2SDLd, [BWPort0,BWPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteCvtPS2PD, [BWPort0,BWPort5], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDLd, [BWPort0,BWPort23], 6, [1,1], 2>;
defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort0,BWPort5], 4, [1,1], 2, 5>;
defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
defm : BWWriteResPair<WriteCvtSD2SS, [BWPort1,BWPort5], 4, [1,1], 2, 5>;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr",
- "(V?)CVTSI642SDrr",
- "(V?)CVTSI2SDrr",
- "(V?)CVTSI2SSrr")>;
+def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PS2PIrr")>;
def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
- CVTSS2SDrm, VCVTSS2SDrm,
- CVTSS2SDrm_Int, VCVTSS2SDrm_Int,
- VPSLLVQrm,
- VPSRLVQrm)>;
+def: InstRW<[BWWriteResGroup59], (instrs VPSLLVQrm, VPSRLVQrm)>;
def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
let Latency = 6;
defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
-defm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>;
+defm : X86WriteRes<WriteCvtI2SD, [HWPort1,HWPort5], 4, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2SDLd, [HWPort1,HWPort23], 9, [1,1], 2>;
defm : HWWriteResPair<WriteCvtI2PD, [HWPort1,HWPort5], 4, [1,1], 2, 6>;
defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1,HWPort5], 6, [1,1], 2, 6>;
defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1,HWPort5], 6, [1,1], 2, 6>; // Unsupported = 1
-defm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>;
+defm : X86WriteRes<WriteCvtI2SS, [HWPort1,HWPort5], 4, [1,1], 2>;
+defm : X86WriteRes<WriteCvtI2SSLd, [HWPort1,HWPort23], 9, [1,1], 2>;
defm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 3, [1], 1, 6>;
defm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1
-defm : HWWriteResPair<WriteCvtSS2SD, [HWPort0,HWPort5], 2, [1,1], 2, 5>;
-defm : HWWriteResPair<WriteCvtPS2PD, [HWPort0,HWPort5], 2, [1,1], 2, 5>;
+defm : X86WriteRes<WriteCvtSS2SD, [HWPort0,HWPort5], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCvtSS2SDLd, [HWPort0,HWPort23], 7, [1,1], 2>;
+defm : X86WriteRes<WriteCvtPS2PD, [HWPort0,HWPort5], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDLd, [HWPort0,HWPort23], 6, [1,1], 2>;
defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort0,HWPort5], 4, [1,1], 2, 6>;
defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort0,HWPort5], 4, [1,1], 2, 6>; // Unsupported = 1
defm : HWWriteResPair<WriteCvtSD2SS, [HWPort1,HWPort5], 4, [1,1], 2, 5>;
STRm,
SYSCALL)>;
-def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>;
-
def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>;
-def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>;
def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 8;
}
def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr,
MMX_CVTTPS2PIrr)>;
-def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTSI(64)?2SDrr",
- "(V?)CVTSI2SSrr")>;
def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> {
let Latency = 11;