[S5PC100] revise cpu/arm_coretex/start.S

diff --git a/board/samsung/tt/lowlevel_init.S b/board/samsung/tt/lowlevel_init.S
index 7521224..961cac7 100644 (file)
--- a/board/samsung/tt/lowlevel_init.S
+++ b/board/samsung/tt/lowlevel_init.S
@@ -51,7 +51,7 @@ _TEXT_BASE:
 
        .globl lowlevel_init
 lowlevel_init:
-       mov     r12, lr
+       mov     r9, lr
 
        /* Disable Watchdog */
        ldr     r0, =S5P_WATCHDOG_BASE(0x0)             @0xEA200000
@@ -142,7 +142,7 @@ interrupt_pending_loop:
        str     r1, [r0, #S5P_MP_6_OFFSET]
        str     r1, [r0, #S5P_MP_7_OFFSET]
 1:
-       mov     lr, r12
+       mov     lr, r9
        mov     pc, lr
 
 wakeup_reset:

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index efff00c..9cf0645 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -82,7 +82,7 @@ int cleanup_before_linux(void)
        /* turn off L2 cache */
        l2cache_disable();
        /* invalidate L2 cache also */
-       //v7_flush_dcache_all(get_device_type());
+       v7_flush_dcache_all(get_device_type());
 #endif
        i = 0;
        /* mem barrier to sync up things */
@@ -95,12 +95,12 @@ int cleanup_before_linux(void)
        return 0;
 }
 
+#ifndef CONFIG_L2_OFF
 void l2cache_enable()
 {
        unsigned long i;
        volatile unsigned int j;
 
-#if 0
        /* ES2 onwards we can disable/enable L2 ourselves */
        if (get_cpu_rev() >= CPU_3XX_ES20) {
                __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -123,8 +123,6 @@ void l2cache_enable()
                __asm__ __volatile__("mov r0, %0":"=r"(i));
                __asm__ __volatile__("mov r12, %0":"=r"(j));
        }
-#endif
-
 }
 
 void l2cache_disable()
@@ -132,7 +130,6 @@ void l2cache_disable()
        unsigned long i;
        volatile unsigned int j;
 
-#if 0
        /* ES2 onwards we can disable/enable L2 ourselves */
        if (get_cpu_rev() >= CPU_3XX_ES20) {
                __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -155,8 +152,8 @@ void l2cache_disable()
                __asm__ __volatile__("mov r0, %0":"=r"(i));
                __asm__ __volatile__("mov r12, %0":"=r"(j));
        }
-#endif
 }
+#endif
 
 static void cache_flush(void)
 {

diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
index f00aaf3..d91b37e 100644 (file)
--- a/cpu/arm_cortexa8/start.S
+++ b/cpu/arm_cortexa8/start.S
@@ -201,14 +201,13 @@ cpu_init_crit:
        /*
         * disable MMU stuff and caches
         */
-       /*
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
        bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
        orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
        orr     r0, r0, #0x00000800     @ set bit 12 (Z---) BTB
        mcr     p15, 0, r0, c1, c0, 0
-       */
+
        /*
         * Jump to board specific initialization...
         * The Mask ROM will have already initialized
@@ -216,9 +215,7 @@ cpu_init_crit:
         * wake up conditions.
         */
        mov     ip, lr                  @ persevere link reg across call
-       mov r9, ip
        bl      lowlevel_init   @ go setup pll,mux,memory
-       mov ip, r9
        mov     lr, ip                  @ restore link
        mov     pc, lr                  @ back to my caller
 /*

diff --git a/include/configs/s5pc100_tt.h b/include/configs/s5pc100_tt.h
index 0b1085c..7cc1f9a 100644 (file)
--- a/include/configs/s5pc100_tt.h
+++ b/include/configs/s5pc100_tt.h
@@ -98,6 +98,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_BAUDRATE                115200
+#define CONFIG_L2_OFF
 
 /***********************************************************
  * Command definition