void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- const DebugLoc &DL, unsigned DestReg,
+ const DebugLoc &DL, Register DestReg,
int64_t Value) const {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
}
}
- return AMDGPU::NoRegister;
+ return Register();
}
static bool shouldReadExec(const MachineInstr &MI) {
}
SGPRUsed = findImplicitSGPRRead(MI);
- if (SGPRUsed != AMDGPU::NoRegister) {
+ if (SGPRUsed) {
// Implicit uses may safely overlap true operands
if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
return !RI.regsOverlap(SGPRUsed, SGPR);
// but still can't use more than one SGPR register
if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
unsigned SGPRCount = 0;
- Register SGPRUsed = AMDGPU::NoRegister;
+ Register SGPRUsed;
for (int OpIdx : {Src0Idx, Src1Idx}) {
if (OpIdx == -1)
// If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
// we need to only have one constant bus use before GFX10.
- bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister;
+ bool HasImplicitSGPR = findImplicitSGPRRead(MI);
if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 &&
Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
int LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
SmallDenseSet<unsigned> SGPRsUsed;
Register SGPRReg = findUsedSGPR(MI, VOP3Idx);
- if (SGPRReg != AMDGPU::NoRegister) {
+ if (SGPRReg) {
SGPRsUsed.insert(SGPRReg);
--ConstantBusLimit;
}
return DstReg;
}
- SmallVector<unsigned, 8> SRegs;
+ SmallVector<Register, 8> SRegs;
for (unsigned i = 0; i < SubRegs; ++i) {
Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
MachineBasicBlock::iterator I = LoopBB.begin();
SmallVector<Register, 8> ReadlanePieces;
- Register CondReg = AMDGPU::NoRegister;
+ Register CondReg;
Register VRsrc = Rsrc.getReg();
unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
Cmp.addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx, 2));
// Combine the comparison results with AND.
- if (CondReg == AMDGPU::NoRegister) // First.
+ if (!CondReg) // First.
CondReg = NewCondReg;
else { // If not the first, we create an AND.
Register AndReg = MRI.createVirtualRegister(BoolXExecRC);
}
bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
- unsigned NewDstReg = AMDGPU::NoRegister;
+ Register NewDstReg;
if (HasDst) {
Register DstReg = Inst.getOperand(0).getReg();
if (DstReg.isPhysical())
// If the operand's class is an SGPR, we can never move it.
Register SGPRReg = findImplicitSGPRRead(MI);
- if (SGPRReg != AMDGPU::NoRegister)
+ if (SGPRReg)
return SGPRReg;
- Register UsedSGPRs[3] = { AMDGPU::NoRegister };
+ Register UsedSGPRs[3] = {Register()};
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
for (unsigned i = 0; i < 3; ++i) {
// TODO: If some of the operands are 64-bit SGPRs and some 32, we should
// prefer those.
- if (UsedSGPRs[0] != AMDGPU::NoRegister) {
+ if (UsedSGPRs[0]) {
if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
SGPRReg = UsedSGPRs[0];
}
- if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
+ if (!SGPRReg && UsedSGPRs[1]) {
if (UsedSGPRs[1] == UsedSGPRs[2])
SGPRReg = UsedSGPRs[1];
}
int &FrameIndex) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
if (!Addr || !Addr->isFI())
- return AMDGPU::NoRegister;
+ return Register();
assert(!MI.memoperands_empty() &&
(*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS);
unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (!MI.mayLoad())
- return AMDGPU::NoRegister;
+ return Register();
if (isMUBUF(MI) || isVGPRSpill(MI))
return isStackAccess(MI, FrameIndex);
if (isSGPRSpill(MI))
return isSGPRStackAccess(MI, FrameIndex);
- return AMDGPU::NoRegister;
+ return Register();
}
unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
if (!MI.mayStore())
- return AMDGPU::NoRegister;
+ return Register();
if (isMUBUF(MI) || isVGPRSpill(MI))
return isStackAccess(MI, FrameIndex);
if (isSGPRSpill(MI))
return isSGPRStackAccess(MI, FrameIndex);
- return AMDGPU::NoRegister;
+ return Register();
}
unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {