In this PR we end up generating an invalid instruction:
adds x1,xzr,#2
because the pattern accepts zero as an operand in the comparison, but the instruction doesn't.
Fix it by adjusting the predicate and constraints.
gcc/ChangeLog:
PR target/99822
* config/aarch64/aarch64.md (sub<mode>3_compare1_imm): Do not allow zero
in operand 1.
gcc/testsuite/ChangeLog:
PR target/99822
* gcc.c-torture/compile/pr99822.c: New test.
(define_insn "sub<mode>3_compare1_imm"
[(set (reg:CC CC_REGNUM)
(compare:CC
- (match_operand:GPI 1 "aarch64_reg_or_zero" "rkZ,rkZ")
+ (match_operand:GPI 1 "register_operand" "rk,rk")
(match_operand:GPI 2 "aarch64_plus_immediate" "I,J")))
(set (match_operand:GPI 0 "register_operand" "=r,r")
(plus:GPI
--- /dev/null
+/* PR target/99822 */
+/* { dg-do assemble } */
+/* { dg-require-effective-target int128 } */
+
+int zt, bm, p5 = 1;
+
+void __attribute__ ((cold))
+l2 (unsigned long int hz)
+{
+ __int128 d9 = 0;
+ unsigned long int *mg = hz ? &hz : (unsigned long int *) &d9;
+
+ while (d9 < 1)
+ {
+ bm = bm > d9;
+ bm = bm == (d9 = bm || hz);
+
+ hz = 0x197000000;
+ d9 = hz * hz;
+
+ while (p5 < 1)
+ {
+ bm = ((hz = 3) ? zt : 0) > 0x1001;
+ if (bm != 0)
+ {
+ __int128 *nd = (__int128 *) bm;
+
+ *nd /= 3;
+ }
+
+ *mg = 0x1001;
+ p5 -= *mg;
+ }
+
+ for (zt = 0; zt >= 0; zt += 2)
+ d9 = 0;
+
+ d9 += 2;
+ }
+}
+