[TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction

Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.

Patch [3/4] in a series to add parsing of predicates and properly parse SVE
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.

Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund

Reviewed By: olista01, sdardis

Subscribers: fhahn, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40362

llvm-svn: 320986

diff --git a/llvm/test/MC/AArch64/SVE/zip1.s b/llvm/test/MC/AArch64/SVE/zip1.s
index f02fa714092e61f5c32b4175e35a5243d23c753e..5dfdc596e19384deaa3274134dfd5583f597bf4c 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/zip1.s
+++ b/llvm/test/MC/AArch64/SVE/zip1.s
@@ -10,95 +10,95 @@
 zip1    z0.b, z0.b, z0.b
 // CHECK-INST: zip1    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x60,0x20,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 60 20 05 <unknown>
 
 zip1    z0.h, z0.h, z0.h
 // CHECK-INST: zip1    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x60,0x60,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 60 60 05 <unknown>
 
 zip1    z0.s, z0.s, z0.s
 // CHECK-INST: zip1    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 60 a0 05 <unknown>
 
 zip1    z0.d, z0.d, z0.d
 // CHECK-INST: zip1    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 60 e0 05 <unknown>
 
 zip1    z31.b, z31.b, z31.b
 // CHECK-INST: zip1    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 63 3f 05 <unknown>
 
 zip1    z31.h, z31.h, z31.h
 // CHECK-INST: zip1    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 63 7f 05 <unknown>
 
 zip1    z31.s, z31.s, z31.s
 // CHECK-INST: zip1    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 63 bf 05 <unknown>
 
 zip1    z31.d, z31.d, z31.d
 // CHECK-INST: zip1    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x63,0xff,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 63 ff 05 <unknown>
 
 zip1    p0.b, p0.b, p0.b
 // CHECK-INST: zip1    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x20,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 40 20 05 <unknown>
 
 zip1    p0.h, p0.h, p0.h
 // CHECK-INST: zip1    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x40,0x60,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 40 60 05 <unknown>
 
 zip1    p0.s, p0.s, p0.s
 // CHECK-INST: zip1    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 40 a0 05 <unknown>
 
 zip1    p0.d, p0.d, p0.d
 // CHECK-INST: zip1    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 40 e0 05 <unknown>
 
 zip1    p15.b, p15.b, p15.b
 // CHECK-INST: zip1    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 41 2f 05 <unknown>
 
 zip1    p15.s, p15.s, p15.s
 // CHECK-INST: zip1    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 41 af 05 <unknown>
 
 zip1    p15.h, p15.h, p15.h
 // CHECK-INST: zip1    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 41 6f 05 <unknown>
 
 zip1    p15.d, p15.d, p15.d
 // CHECK-INST: zip1    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x41,0xef,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 41 ef 05 <unknown>

diff --git a/llvm/test/MC/AArch64/SVE/zip2.s b/llvm/test/MC/AArch64/SVE/zip2.s
index f3002d3e446f4b27f964b3c143724ef0a26668ab..d3e6126e2d7497b72ecb3ab31b158682c2e1dd0b 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/zip2.s
+++ b/llvm/test/MC/AArch64/SVE/zip2.s
@@ -10,95 +10,95 @@
 zip2    z0.b, z0.b, z0.b
 // CHECK-INST: zip2    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x64,0x20,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 64 20 05 <unknown>
 
 zip2    z0.h, z0.h, z0.h
 // CHECK-INST: zip2    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x64,0x60,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 64 60 05 <unknown>
 
 zip2    z0.s, z0.s, z0.s
 // CHECK-INST: zip2    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 64 a0 05 <unknown>
 
 zip2    z0.d, z0.d, z0.d
 // CHECK-INST: zip2    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 64 e0 05 <unknown>
 
 zip2    z31.b, z31.b, z31.b
 // CHECK-INST: zip2    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 67 3f 05 <unknown>
 
 zip2    z31.h, z31.h, z31.h
 // CHECK-INST: zip2    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 67 7f 05 <unknown>
 
 zip2    z31.s, z31.s, z31.s
 // CHECK-INST: zip2    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 67 bf 05 <unknown>
 
 zip2    z31.d, z31.d, z31.d
 // CHECK-INST: zip2    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x67,0xff,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ff 67 ff 05 <unknown>
 
 zip2    p0.b, p0.b, p0.b
 // CHECK-INST: zip2    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x44,0x20,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 44 20 05 <unknown>
 
 zip2    p0.h, p0.h, p0.h
 // CHECK-INST: zip2    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x44,0x60,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 44 60 05 <unknown>
 
 zip2    p0.s, p0.s, p0.s
 // CHECK-INST: zip2    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 44 a0 05 <unknown>
 
 zip2    p0.d, p0.d, p0.d
 // CHECK-INST: zip2    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: 00 44 e0 05 <unknown>
 
 zip2    p15.b, p15.b, p15.b
 // CHECK-INST: zip2    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 45 2f 05 <unknown>
 
 zip2    p15.h, p15.h, p15.h
 // CHECK-INST: zip2    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 45 6f 05 <unknown>
 
 zip2    p15.s, p15.s, p15.s
 // CHECK-INST: zip2    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 45 af 05 <unknown>
 
 zip2    p15.d, p15.d, p15.d
 // CHECK-INST: zip2    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x45,0xef,0x05]
-// CHECK-ERROR: invalid predicate register
+// CHECK-ERROR: invalid operand for instruction
 // CHECK-UNKNOWN: ef 45 ef 05 <unknown>

diff --git a/llvm/test/MC/AArch64/armv8.3a-complex.s b/llvm/test/MC/AArch64/armv8.3a-complex.s
index 70dd479235c1308fccd47d731dafb7b275ba1721..1a4975b3e892763f8964af88eec2d964ecebad78 100644 (file)
--- a/llvm/test/MC/AArch64/armv8.3a-complex.s
+++ b/llvm/test/MC/AArch64/armv8.3a-complex.s
@@ -133,9 +133,11 @@
 
 // Invalid indices
   fcmla v0.4h, v1.4h, v2.h[2], #0
-// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
+// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
+// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
   fcmla v0.8h, v1.8h, v2.h[4], #0
-// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].
+// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction
+// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3].
   fcmla v0.4s, v1.4s, v2.s[2], #0
 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1].
 

diff --git a/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s b/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s
index 4b725135ef14e711a3a032dc2cb47f7d5970ef5b..3318831b81c1f2e04010d7936292c9c5499e1d51 100644 (file)
--- a/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s
+++ b/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s
@@ -19,51 +19,51 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        cachee    31, 255($7)          # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset
-        cachee    0, -256($4)          # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset
-        cachee    5, -140($4)          # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset
-        lbe       $10,-256($25)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lbe       $13,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lbe       $11,146($14)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lbue      $13,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lbue      $13,255($v0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lbue      $13,-190($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhe       $13,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhe       $12,255($s0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhe       $13,81($s0)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhue      $s2,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhue      $s2,255($v1)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhue      $s6,-168($v0)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lle       $v0,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lle       $v1,255($s3)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lle       $v1,-71($s6)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwe       $15,255($a2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwe       $13,-256($a2)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwe       $15,-200($a1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwle      $s6,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwle      $s7,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwle      $s7,-176($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,255($gp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-256($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-176($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        prefe     14, -256($2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        prefe     11, 255($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        prefe     14, -37($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sbe       $s1,255($11)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sbe       $s1,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sbe       $s3,0($14)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sce       $9,255($s2)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sce       $12,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sce       $13,-31($s7)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        she       $14,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        she       $14,-256($15)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        she       $9,235($11)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swe       $ra,255($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swe       $ra,-256($sp)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swe       $ra,-53($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $9,255($s1)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $10,-256($s3)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $8,131($s5)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s4,255($13)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s4,-256($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s2,86($14)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        cachee    31, 255($7)          # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        cachee    0, -256($4)          # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+        cachee    5, -140($4)          # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+        lbe       $10,-256($25)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lbe       $13,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lbe       $11,146($14)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lbue      $13,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lbue      $13,255($v0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lbue      $13,-190($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe       $13,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe       $12,255($s0)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe       $13,81($s0)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue      $s2,-256($v1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue      $s2,255($v1)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue      $s6,-168($v0)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lle       $v0,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lle       $v1,255($s3)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lle       $v1,-71($s6)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwe       $15,255($a2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwe       $13,-256($a2)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwe       $15,-200($a1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s6,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s7,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s7,-176($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,255($gp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-256($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-176($gp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        prefe     14, -256($2)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        prefe     11, 255($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        prefe     14, -37($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sbe       $s1,255($11)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sbe       $s1,-256($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sbe       $s3,0($14)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sce       $9,255($s2)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sce       $12,-256($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sce       $13,-31($s7)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        she       $14,255($15)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        she       $14,-256($15)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        she       $9,235($11)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swe       $ra,255($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swe       $ra,-256($sp)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swe       $ra,-53($sp)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $9,255($s1)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $10,-256($s3)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $8,131($s5)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s4,255($13)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s4,-256($13)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s2,86($14)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/eva/invalid.s b/llvm/test/MC/Mips/eva/invalid.s
index 406d940c8a92868582de49d1b0a78183385087a6..5c4cc3ddf631aedc4c40008f53e550004780f3ab 100644 (file)
--- a/llvm/test/MC/Mips/eva/invalid.s
+++ b/llvm/test/MC/Mips/eva/invalid.s
@@ -5,31 +5,31 @@
 # RUN: FileCheck %s < %t1
 
     .set noat
-    cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
-    cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
-    prefe -1, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-    prefe 32, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+    cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+    cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+    prefe -1, 255($7)  # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+    prefe 32, 255($7)  # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
     lle $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    lle $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    lle $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    lle $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lle $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lle $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lle $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
     lwe $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    lwe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    lwe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    lwe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    lwe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lwe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    lwe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
     sbe $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    sbe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    sbe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    sbe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sbe $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sbe $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sbe $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
     sce $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    sce $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    sce $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    sce $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    sce $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sce $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    sce $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
     she $33, 8($5)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    she $4, 8($33)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    she $4, 512($5)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    she $4, -513($5)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    she $4, 8($33)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    she $4, 512($5)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    she $4, -513($5)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
     swe $33, 8($4)     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-    swe $5, 8($34)     # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    swe $5, 512($4)    # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
-    swe $5, -513($4)   # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
+    swe $5, 8($34)     # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    swe $5, 512($4)    # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+    swe $5, -513($4)   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/eva/invalid_R6.s b/llvm/test/MC/Mips/eva/invalid_R6.s
index b3242e6ffd720b0693daf0802662baf7a7abdb16..7e99bc28c3154d57365fbe2c3791a3de88165061 100644 (file)
--- a/llvm/test/MC/Mips/eva/invalid_R6.s
+++ b/llvm/test/MC/Mips/eva/invalid_R6.s
@@ -6,18 +6,18 @@
 # RUN: FileCheck %s < %t1
 
         .set noat
-        lwle      $s6,255($15)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwle      $s7,-256($10)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwle      $s7,-176($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,255($gp)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-256($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-176($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $9,255($s1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $10,-256($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $8,131($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s4,255($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s4,-256($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s2,86($14)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s6,255($15)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s7,-256($10)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwle      $s7,-176($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,255($gp)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-256($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-176($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $9,255($s1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $10,-256($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $8,131($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s4,255($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s4,-256($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s2,86($14)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lle       $33, 8($5)         # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
         lle       $4, 8($33)         # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset
         lle       $4, 512($5)        # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset

diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
index d1ba873809dbd6e167bb1fb15962820e836b29eb..d43ca766fa0cb62b029cf4d2430f2838e05ed640 100644 (file)
--- a/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
@@ -4,4 +4,4 @@
 
   .set noat
   wrdsp $5, 128            # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
+  wrdsp $5, -1             # CHECK: :[[@LINE]]:13: error: expected 7-bit unsigned immediate

diff --git a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
index 8d39498bf90d240cba71a55ad7fab1b593ddd6fa..3e4837885a1920ce9138660503a66f9c7e11a461 100644 (file)
--- a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
@@ -6,8 +6,8 @@
   # the diagnostic for the 20-bit form. This isn't exactly wrong but it is
   # misleading. Ideally, we'd emit every way to achieve a valid match instead
   # of picking only one.
-  sdbbp -1            # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
+  sdbbp -1            # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
   sdbbp 1024          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  syscall -1          # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
-  syscall $4          # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
+  syscall -1          # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  syscall $4          # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
   syscall 1024        # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
index 823d3f9a77bc6dc40e1fd2a0aa155473407c4822..33c5d6595faf4516d0ca2eca5086c0856fb64cd0 100644 (file)
--- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
@@ -7,38 +7,20 @@
   # the diagnostic for the 10-bit form. This isn't exactly wrong but it is
   # misleading. Ideally, we'd emit every way to achieve a valid match instead
   # of picking only one.
-  teq $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  teq $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   teq $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tge $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tge $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tge $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tgeu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tgeu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
   tgeu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tlt $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tlt $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tlt $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tltu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tltu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
   tltu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tne $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tne $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
   tne $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  syscall -1               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
-  syscall $4               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
   syscall 1024             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ldc2 $1, -2049($12)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ldc2 $1, 2048($12)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   lwc2 $1, -2049($4)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   lwc2 $1, 2048($4)        # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   sdc2 $1, -2049($16)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   sdc2 $1, 2048($16)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   swc2 $1, -2049($17)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   swc2 $1, 2048($17)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  swc2 $1, 777($32)        # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
   lwc2 $11, -1025($12)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   lwc2 $11, 1024($12)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s
index 22ec6395cbad658061f774247ebf27b66249eb37..218202bc505e058311d751f1d1300a9c0f6b378a 100644 (file)
--- a/llvm/test/MC/Mips/micromips32r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid.s
@@ -351,3 +351,21 @@
   bnezc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bnezc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bnezc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
+  teq $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  teq $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tge $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tge $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tgeu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
+  tgeu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
+  tlt $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tlt $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tltu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
+  tltu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate
+  tne $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  tne $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate
+  syscall -1               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  syscall $4               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
+  lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
+  sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset
+  swc2 $1, 777($32)        # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
index 5897fb84a2012c0fe12940703fd4e628397fec1f..1b0bcd4f50bb0af0857afea02f1821ba492f6e6b 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s
@@ -6,11 +6,11 @@
 # RUN: FileCheck %s < %t1
 
        .set noat
-        ldc2      $8,-21181($at)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        ldc2      $8,-1024($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $8,-21181($at)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $8,-1024($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldc3      $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sc        $t7,18904($s3)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sdc2      $20,23157($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        sdc2      $20,-1024($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ll        $v0,-7321($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sc        $t7,18904($s3)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,23157($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,-1024($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdc3      $12,5835($t2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
index d140b258533aa16a22d2c43c3e0c8d41c7c2af64..b927235e7ca9640f9dfdd275c6130ddc91865817 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s
@@ -6,14 +6,14 @@
 # RUN: FileCheck %s < %t1
 
        .set noat
-        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldl       $24,-4167($24)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $14,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips3.s b/llvm/test/MC/Mips/mips1/invalid-mips3.s
index 42e390df470a3a5e50e393e0b23a0dd258b7a30d..6a2543424b80cbc08677fd98438782d16d4ca5e7 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips3.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips3.s
@@ -54,8 +54,8 @@
         floor.l.s $f12,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.d $f14,$f11         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.s $f8,$f9           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
+        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
         round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
index 98f34d857a5253b1d7a597f740b19faeb391395d..61c9ccaa2c2c728cce99e343e554fca41f8d28f7 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s
@@ -8,14 +8,14 @@
        .set noat
         bc1fl     $fcc7,27          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bc1tl     $fcc7,27          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc2      $8,-21181($at)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldl       $24,-4167($24)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $14,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ll        $v0,-7321($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sc        $15,18904($s3)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        scd       $15,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,23157($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc2      $20,-1024($s2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4.s b/llvm/test/MC/Mips/mips1/invalid-mips4.s
index e99fb6628e6cb8db53918a13470c953621ba7a40..def3a14e601d76cf5aaec7cca59d6370c7d81257 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips4.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips4.s
@@ -69,8 +69,8 @@
         movz      $a1,$s6,$9        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movz.d    $f12,$f29,$9      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movz.s    $f25,$f7,$v1      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
+        lld       $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwu       $s3,-24086($v1)   # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
         round.l.d $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s
index f909c07f15f1c393644581c9fe7f090930c0fc65..1d7a864d2f5610420d9a609841d0ff40632d8abd 100644 (file)
--- a/llvm/test/MC/Mips/mips1/invalid-mips5.s
+++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s
@@ -88,5 +88,5 @@
         sdxc1     $f11,$a2($t2)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         suxc1     $f12,$k1($t1)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swxc1     $f19,$t0($k0)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        ldc1      $f11,16391($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        sdc1      $f31,30574($t5)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
+        ldc1      $f11,16391($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc1      $f31,30574($t5)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
index 9aa17b6695b7a0a6cfaf171d9452051e5b1c942c..e99d74ca0f676126096eec7d9d742aa5388d8ec6 100644 (file)
--- a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s
@@ -9,6 +9,6 @@
         dmult     $s7,$a5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldl       $t8,-4167($t8)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldr       $t2,-30358($s4)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        scd       $t3,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        scd       $t3,-8243($sp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdl       $a3,-20961($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $a7,-20423($t0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3.s b/llvm/test/MC/Mips/mips2/invalid-mips3.s
index b85204379c7405a931948c5ceda2c3512a925629..4bbd486bfd12eb0cf2aa288801f55c618817dfeb 100644 (file)
--- a/llvm/test/MC/Mips/mips2/invalid-mips3.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips3.s
@@ -50,8 +50,8 @@
         eret                         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.l.d  $f26,$f7          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.l.s  $f12,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lld        $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lwu        $s3,-24086($v1)   # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
+        lld        $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwu        $s3,-24086($v1)   # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
         round.l.d  $f12,$f1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.l.s  $f25,$f5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.l.d   $f23,$f23        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
index 5ced993c2e11aea259d5ca4378c85cc361d34317..e46aac67cdc0bbd2225e99cbbc1da97f5e192118 100644 (file)
--- a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s
@@ -8,6 +8,6 @@
        .set noat
         bc1fl     $fcc7,27        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
         bc1tl     $fcc7,27        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
-        scd       $15,-8243($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        scd       $15,-8243($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdl       $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdr       $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4.s b/llvm/test/MC/Mips/mips2/invalid-mips4.s
index 123235eb00b2aabfe89bba5a5e6b69af1452a520..04348925cee8e37ade2b19009deaa5becb5f3a78 100644 (file)
--- a/llvm/test/MC/Mips/mips2/invalid-mips4.s
+++ b/llvm/test/MC/Mips/mips2/invalid-mips4.s
@@ -48,7 +48,7 @@
         floor.l.s $f12,$f5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ldxc1     $f8,$s7($15)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         lwxc1     $f12,$s1($s8)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        lwu       $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
+        lwu       $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
         movf      $gp,$8,$fcc0    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movf      $gp,$8,$fcc7    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         movf.d    $f6,$f11,$fcc0  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
index deafbb02eca4bcfe4c5e3c36660f5bc06739e0cd..6d569d12b396786d63367df19387d2a5b33db2c2 100644 (file)
--- a/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
+++ b/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s
@@ -11,8 +11,8 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $24, 5($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $24, 5($3)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
index b26cc4e23283f9e98ad4eedce229e9836aa48dac..aa911be15cb7f364e7901b24267e6a025bab187a 100644 (file)
--- a/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
+++ b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s
@@ -11,13 +11,13 @@
         bc1any4t  $fcc2,4             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
         ldc2 $1, -2049($12)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         ldc2 $1, 2048($12)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        ldc2 $1, 1023($32)            # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+        ldc2 $1, 1023($32)            # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
         lwc2 $1, -2049($4)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         lwc2 $1, 2048($4)             # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        lwc2 $1, 16($32)              # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+        lwc2 $1, 16($32)              # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
         sdc2 $1, -2049($16)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         sdc2 $1, 2048($16)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        sdc2 $1, 8($32)               # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+        sdc2 $1, 8($32)               # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset
         swc2 $1, -2049($17)           # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         swc2 $1, 2048($17)            # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
-        swc2 $1, 777($32)             # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
+        swc2 $1, 777($32)             # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset

diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s
index fac106fc949a2d13042382d46b863d350e85830a..cb950cbd08b919c677cd90607b910a1342158a34 100644 (file)
--- a/llvm/test/MC/Mips/mips32r6/invalid.s
+++ b/llvm/test/MC/Mips/mips32r6/invalid.s
@@ -27,17 +27,17 @@ local_label:
         lhu $35, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhue $36, 8($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, 8($34)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhu $4, 8($35)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lh  $2, 65536($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lhu $4, 65536($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/mips64/invalid-mips64r2.s b/llvm/test/MC/Mips/mips64/invalid-mips64r2.s
index 4d8411634f224bb0e6ffe8eec36351cc72534c68..d8730af4388ec9d4fe03255189c9b81e59922604 100644 (file)
--- a/llvm/test/MC/Mips/mips64/invalid-mips64r2.s
+++ b/llvm/test/MC/Mips/mips64/invalid-mips64r2.s
@@ -29,13 +29,13 @@
         seb       $25,$15             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         seh       $v1,$12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         wsbh      $k1,$9              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        dins $2, $3, -1, 1            # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
-        dins $2, $3, 64, 1            # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
-        dinsm $2, $3, -1, 1           # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
-        dinsm $2, $3, 32, 1           # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
-        dinsm $2, $3, 31, 0           # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64
-        dinsm $2, $3, 31, 65          # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64
-        dinsu $2, $3, 31, 1           # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
-        dinsu $2, $3, 64, 1           # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
-        dinsu $2, $3, 63, 0           # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
-        dinsu $2, $3, 32, 33          # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32
+        dins $2, $3, -1, 1            # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+        dins $2, $3, 64, 1            # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+        dinsm $2, $3, -1, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        dinsm $2, $3, 32, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        dinsm $2, $3, 31, 0           # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+        dinsm $2, $3, 31, 65          # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+        dinsu $2, $3, 31, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        dinsu $2, $3, 64, 1           # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+        dinsu $2, $3, 63, 0           # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+        dinsu $2, $3, 32, 33          # CHECK: :[[@LINE]]:27: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
index 816cc1f8c6cdcc39644a621ab25087144a79feb2..06d95fd8665b99ca618267e3dff1e2f81e3627d7 100644 (file)
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s
@@ -11,7 +11,7 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
index bf2d5fa988b6fb9137d0753a193ae0b418cc072d..a111726fca38cbf400fb71efaeb64fc47c9fd9ce 100644 (file)
--- a/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s
@@ -17,7 +17,7 @@
         lwr       $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swl       $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swr       $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lwle      $s4,-4231($15)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwre      $zero,-19147($gp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swle      $15,13694($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        swre      $s1,-26590($14)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s
index a19181b723f95daf5eb8f285b1a50dd9b99f82bd..a740537118245524b0ccac317862b0a036a2b01a 100644 (file)
--- a/llvm/test/MC/Mips/mips64r6/invalid.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid.s
@@ -57,17 +57,17 @@ local_label:
         lhu $35, 8($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhue $36, 8($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, 8($34)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, 8($33)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhu $4, 8($35)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, 8($37)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lh  $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lh  $2, 65536($4)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhe $4, -512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhe $4, 512($2)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
         lhu $4, 65536($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
+        lhue $4, -512($2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lhue $4, 512($2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved
         bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/llvm/test/MC/Mips/msa/invalid.s b/llvm/test/MC/Mips/msa/invalid.s
index 78b1949d0ae531d02f4df05652358d41e1f5147b..ffb5b368d70126ca0718fa6278ca8cd3799caad3 100644 (file)
--- a/llvm/test/MC/Mips/msa/invalid.s
+++ b/llvm/test/MC/Mips/msa/invalid.s
@@ -107,22 +107,22 @@
     copy_s.h $2, $w9[8]      # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
     copy_s.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
     copy_s.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
-    copy_s.d $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
-    copy_s.d $2, $w9[2]      # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
+    copy_s.d $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+    copy_s.d $2, $w9[2]      # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
     copy_u.b $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
     copy_u.b $2, $w9[16]     # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
     copy_u.h $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
     copy_u.h $2, $w9[8]      # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
-    copy_u.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
-    copy_u.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate
+    copy_u.w $2, $w9[-1]     # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+    copy_u.w $2, $w9[4]      # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
     insert.b $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insert.b $w9[16], $2     # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insert.h $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
     insert.h $w9[8], $2      # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
     insert.w $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
     insert.w $w9[4], $2      # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
-    insert.d $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
-    insert.d $w9[2], $2      # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate
+    insert.d $w9[-1], $2     # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+    insert.d $w9[2], $2      # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
     insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
     insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate

diff --git a/llvm/test/MC/Mips/target-soft-float.s b/llvm/test/MC/Mips/target-soft-float.s
index f532cdf2ed972fa47042d89f0b0c20960be06337..5865d5ab12696c26937c442e9a331b60f2da39c8 100644 (file)
--- a/llvm/test/MC/Mips/target-soft-float.s
+++ b/llvm/test/MC/Mips/target-soft-float.s
@@ -269,10 +269,10 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   ldc1       $f2, 16($7)
   # FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
   lwc1       $f2, 16($7)
   # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
   madd.s     $f2, $f2, $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   mfc1       $7, $f2
@@ -313,7 +313,7 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   sdc1       $f2, 16($7)
   # FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
   sqrt.d     $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   sqrt.s     $f2, $f2
@@ -324,7 +324,7 @@ foo:
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   swc1       $f2, 16($7)
   # FIXME: SWC1 is correctly rejected but the wrong error message is emitted.
-  # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset
+  # 32: :[[@LINE-2]]:19: error: invalid operand for instruction
   trunc.w.d  $f2, $f2
   # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
   trunc.w.s  $f2, $f2

diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 1a820a54c60584449d639a924eedc68c039559c3..0143d916a00c0bc9bb393eeb1774298415b25083 100644 (file)
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -3269,7 +3269,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "  for (const MatchEntry *it = MnemonicRange.first, "
      << "*ie = MnemonicRange.second;\n";
   OS << "       it != ie; ++it) {\n";
-
+  OS << "    bool HasRequiredFeatures =\n";
+  OS << "      (AvailableFeatures & it->RequiredFeatures) == "
+        "it->RequiredFeatures;\n";
   OS << "    DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match opcode \"\n";
   OS << "                                          << MII.getName(it->Opcode) << \"\\n\");\n";
 
@@ -3360,7 +3362,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "        }\n";
   OS << "        // If the target matcher returned a specific error code use\n";
   OS << "        // that, else use the one from the generic matcher.\n";
-  OS << "        if (TargetDiag != Match_InvalidOperand)\n";
+  OS << "        if (TargetDiag != Match_InvalidOperand && "
+        "HasRequiredFeatures)\n";
   OS << "          Diag = TargetDiag;\n";
   OS << "      }\n";
   OS << "      // If current formal operand wasn't matched and it is optional\n"
@@ -3402,7 +3405,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
     OS << "      // target predicate, that diagnostic is preferred.\n";
     OS << "      if (!HadMatchOtherThanPredicate &&\n";
     OS << "          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
-    OS << "        if (Diag != Match_InvalidOperand || ErrorInfo != ActualIdx)\n";
+    OS << "        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
+          "!= Match_InvalidOperand))\n";
     OS << "          RetCode = Diag;\n";
     OS << "        ErrorInfo = ActualIdx;\n";
     OS << "      }\n";
@@ -3423,8 +3427,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
   OS << "    }\n";
 
   // Emit check that the required features are available.
-  OS << "    if ((AvailableFeatures & it->RequiredFeatures) "
-     << "!= it->RequiredFeatures) {\n";
+  OS << "    if (!HasRequiredFeatures) {\n";
   if (!ReportMultipleNearMisses)
     OS << "      HadMatchOtherThanFeatures = true;\n";
   OS << "      uint64_t NewMissingFeatures = it->RequiredFeatures & "