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x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
author
Tony Luck
<tony.luck@intel.com>
Fri, 21 Jan 2022 17:47:38 +0000
(09:47 -0800)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Tue, 1 Feb 2022 16:27:06 +0000
(17:27 +0100)
commit
e464121f2d40eabc7d11823fb26db807ce945df4
upstream.
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes:
dc6b025de95b
("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link:
https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/kernel/cpu/mce/intel.c
patch
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diff --git
a/arch/x86/kernel/cpu/mce/intel.c
b/arch/x86/kernel/cpu/mce/intel.c
index
bb9a46a
..
baafbb3
100644
(file)
--- a/
arch/x86/kernel/cpu/mce/intel.c
+++ b/
arch/x86/kernel/cpu/mce/intel.c
@@
-486,6
+486,7
@@
static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM: