AArch64: Add FLAG for tbl/tbx intrinsics [PR94442]

2020-11-10  Zhiheng Xie  <xiezhiheng@huawei.com>
	    Nannan Zheng  <zhengnannan@huawei.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
	for tbl/tbx intrinsics.

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 09f275c..cb05aad 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -545,28 +545,28 @@
   VAR1 (BINOPP, crypto_pmull, 0, NONE, v2di)
 
   /* Implemented by aarch64_tbl3<mode>.  */
-  VAR1 (BINOP, tbl3, 0, ALL, v8qi)
-  VAR1 (BINOP, tbl3, 0, ALL, v16qi)
+  VAR1 (BINOP, tbl3, 0, NONE, v8qi)
+  VAR1 (BINOP, tbl3, 0, NONE, v16qi)
 
   /* Implemented by aarch64_qtbl3<mode>.  */
-  VAR1 (BINOP, qtbl3, 0, ALL, v8qi)
-  VAR1 (BINOP, qtbl3, 0, ALL, v16qi)
+  VAR1 (BINOP, qtbl3, 0, NONE, v8qi)
+  VAR1 (BINOP, qtbl3, 0, NONE, v16qi)
 
   /* Implemented by aarch64_qtbl4<mode>.  */
-  VAR1 (BINOP, qtbl4, 0, ALL, v8qi)
-  VAR1 (BINOP, qtbl4, 0, ALL, v16qi)
+  VAR1 (BINOP, qtbl4, 0, NONE, v8qi)
+  VAR1 (BINOP, qtbl4, 0, NONE, v16qi)
 
   /* Implemented by aarch64_tbx4<mode>.  */
-  VAR1 (TERNOP, tbx4, 0, ALL, v8qi)
-  VAR1 (TERNOP, tbx4, 0, ALL, v16qi)
+  VAR1 (TERNOP, tbx4, 0, NONE, v8qi)
+  VAR1 (TERNOP, tbx4, 0, NONE, v16qi)
 
   /* Implemented by aarch64_qtbx3<mode>.  */
-  VAR1 (TERNOP, qtbx3, 0, ALL, v8qi)
-  VAR1 (TERNOP, qtbx3, 0, ALL, v16qi)
+  VAR1 (TERNOP, qtbx3, 0, NONE, v8qi)
+  VAR1 (TERNOP, qtbx3, 0, NONE, v16qi)
 
   /* Implemented by aarch64_qtbx4<mode>.  */
-  VAR1 (TERNOP, qtbx4, 0, ALL, v8qi)
-  VAR1 (TERNOP, qtbx4, 0, ALL, v16qi)
+  VAR1 (TERNOP, qtbx4, 0, NONE, v8qi)
+  VAR1 (TERNOP, qtbx4, 0, NONE, v16qi)
 
   /* Builtins for ARMv8.1-A Adv.SIMD instructions.  */