Fixed VME result offset issue for IVB.

Signe-off-by: Zhou Chang <chang.zhou@intel.com>
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/shaders/vme/inter_frame.asm b/src/shaders/vme/inter_frame.asm
index 0a4db66..fbcfa7d 100644 (file)
--- a/src/shaders/vme/inter_frame.asm
+++ b/src/shaders/vme/inter_frame.asm
@@ -27,10 +27,18 @@ mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
  */
 /* m0 */        
 mul  (2) tmp_reg0.8<1>:UW       orig_xy_ub<2,2,1>:UB 16:UW {align1};    /* Source =  (x, y) * 16 */
+        
+#ifdef DEV_SNB        
 mul  (2) tmp_reg0.0<1>:UW       orig_xy_ub<2,2,1>:UB 16:UW {align1};   
 add  (1) tmp_reg0.0<1>:W        tmp_reg0.0<2,2,1>:W -16:W {align1};            /* Reference = (x-16,y-12)-(x+32,y+24) */
 add  (1) tmp_reg0.2<1>:W        tmp_reg0.2<2,2,1>:W -12:W {align1};
+#else
+mov  (1) tmp_reg0.0<1>:W        -16:W {align1} ;                /* Reference = (x-16,y-12)-(x+32,y+24) */
+mov  (1) tmp_reg0.2<1>:W        -12:W {align1} ;
+#endif
+        
 mov  (1) tmp_reg0.12<1>:UD      INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1};    /* 16x16 Source, 1/4 pixel, harr */
+        
 
 mov  (1) tmp_reg0.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
 mov  (1) tmp_reg0.22<1>:UW      REF_REGION_SIZE {align1};               /* Reference Width&Height, 32x32 */
@@ -74,10 +82,13 @@ mul  (1) tmp_reg3.8<1>:UD       tmp_reg3.8<0,1,0>:UD 0x4:UD {align1};
 mov  (1) tmp_reg3.20<1>:UB      thread_id_ub {align1};                  /* dispatch id */
 mov  (8) msg_reg0.0<1>:UD       tmp_reg3.0<8,8,1>:UD {align1};
 
+#ifdef DEV_SNB        
 mov  (2) tmp_reg3.0<1>:UW       vme_wb1.0<2,2,1>:UB  {align1};
 add  (1) tmp_reg3.0<1>:W        tmp_reg3.0<2,2,1>:W -64:W {align1};
 add  (1) tmp_reg3.2<1>:W        tmp_reg3.2<2,2,1>:W -48:W {align1}; 
-        
+#else
+mov  (2) tmp_reg3.0<1>:UW       vme_wb1.0<2,2,1>:B  {align1};        
+#endif       
         
 mov  (8) msg_reg1.0<1>:UD       tmp_reg3.0<8,8,0>:UD   {align1};
 

diff --git a/src/shaders/vme/inter_frame.g7b b/src/shaders/vme/inter_frame.g7b
index 03d8c90..82e48d2 100644 (file)
--- a/src/shaders/vme/inter_frame.g7b
+++ b/src/shaders/vme/inter_frame.g7b
@@ -1,9 +1,8 @@
    { 0x00800001, 0x24000061, 0x00000000, 0x00000000 },
    { 0x00800001, 0x24400061, 0x00000000, 0x00000000 },
    { 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 },
-   { 0x00200041, 0x24002e29, 0x004500a0, 0x00100010 },
-   { 0x00000040, 0x24003dad, 0x00450400, 0xfff0fff0 },
-   { 0x00000040, 0x24023dad, 0x00450402, 0xfff4fff4 },
+   { 0x00000001, 0x240001ed, 0x00000000, 0xfff0fff0 },
+   { 0x00000001, 0x240201ed, 0x00000000, 0xfff4fff4 },
    { 0x00000001, 0x240c0061, 0x00000000, 0x7e203000 },
    { 0x00000001, 0x24140231, 0x00000014, 0x00000000 },
    { 0x00000001, 0x24160169, 0x00000000, 0x28302830 },
@@ -20,9 +19,7 @@
    { 0x00000041, 0x24680c21, 0x00000468, 0x00000004 },
    { 0x00000001, 0x24740231, 0x00000014, 0x00000000 },
    { 0x00600001, 0x28000021, 0x008d0460, 0x00000000 },
-   { 0x00200001, 0x24600229, 0x004501a0, 0x00000000 },
-   { 0x00000040, 0x24603dad, 0x00450460, 0xffc0ffc0 },
-   { 0x00000040, 0x24623dad, 0x00450462, 0xffd0ffd0 },
+   { 0x00200001, 0x246002a9, 0x004501a0, 0x00000000 },
    { 0x00600001, 0x28200021, 0x008c0460, 0x00000000 },
    { 0x00600001, 0x28400021, 0x008c0460, 0x00000000 },
    { 0x0a800031, 0x20001cac, 0x00000800, 0x060a0303 },