#define GET_SUBTARGETINFO_CTOR
#include "RISCVGenSubtargetInfo.inc"
+static cl::opt<unsigned> RVVVectorBitsMax(
+ "riscv-v-vector-bits-max",
+ cl::desc("Assume V extension vector registers are at most this big, "
+ "with zero meaning no maximum size is assumed."),
+ cl::init(0), cl::Hidden);
+
static cl::opt<unsigned> RVVVectorBitsMin(
"riscv-v-vector-bits-min",
cl::desc("Assume V extension vector registers are at least this big, "
"Fractional LMUL values are not supported."),
cl::init(8), cl::Hidden);
-static cl::opt<unsigned> VectorBitsMax(
- "riscv-vector-bits-max",
- cl::desc("Assume RISC-V vector registers are at most this big"),
- cl::init(0), cl::Hidden);
-
void RISCVSubtarget::anchor() {}
RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
return *this;
}
-unsigned RISCVSubtarget::getMaxVectorSizeInBits() const {
- assert(HasStdExtV && "Tried to get vector length without V support!");
- return VectorBitsMax;
-}
-
RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
StringRef TuneCPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
return RegBankInfo.get();
}
+unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
+ assert(hasStdExtV() && "Tried to get vector length without V support!");
+ if (RVVVectorBitsMax == 0)
+ return 0;
+ assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
+ "V extension requires vector length to be at least 128 and a power of "
+ "2!");
+ assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
+ "Minimum V extension vector length should not be larger than its "
+ "maximum!");
+ unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
+ return PowerOf2Floor(Max < 128 ? 0 : Max);
+}
+
unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
assert(hasStdExtV() &&
"Tried to get vector length without V extension support!");
(RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
"V extension requires vector length to be at least 128 and a power of "
"2!");
- return PowerOf2Floor(RVVVectorBitsMin < 128 ? 0 : RVVVectorBitsMin);
+ assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
+ "Minimum V extension vector length should not be larger than its "
+ "maximum!");
+ unsigned Min = RVVVectorBitsMin;
+ if (RVVVectorBitsMax != 0)
+ Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
+ return PowerOf2Floor(Min < 128 ? 0 : Min);
}
unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
return UserReservedRegister[i];
}
- unsigned getMaxVectorSizeInBits() const;
protected:
// GlobalISel related APIs.
// Return the known range for the bit length of RVV data registers. A value
// of 0 means nothing is known about that particular limit beyond what's
// implied by the architecture.
+ unsigned getMaxRVVVectorSizeInBits() const;
unsigned getMinRVVVectorSizeInBits() const;
unsigned getLMULForFixedLengthVector(MVT VT) const;
unsigned getMaxLMULForFixedLengthVectors() const;