powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index e13bb53..7c63f84 100644 (file)
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
        SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-       SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-       SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-       SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
        SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c69dfe4..4b2ef4e 100644 (file)
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -129,107 +129,34 @@ phys_size_t fixed_sdram (void)
 
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       struct fsl_pci_info pci_info[3];
-       u32 devdisr, pordevsr, io_sel, temp32;
-       int first_free_busno = 0;
-       int num = 0;
+       struct pci_controller *hose;
 
-       int pcie_ep, pcie_configured;
+       fsl_pcie_init_board(0);
 
-       devdisr = in_be32(&gur->devdisr);
-       pordevsr = in_be32(&gur->pordevsr);
-       io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+       hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
 
-       debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+       if (hose) {
+               u32 temp32;
+               u8 uli_busno = hose->first_busno + 2;
 
-       puts("\n");
-#ifdef CONFIG_PCIE3
-       pcie_configured = is_serdes_configured(PCIE3);
-
-       if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-               SET_STD_PCIE_INFO(pci_info[num], 3);
-               pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
-               printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                                       &pcie3_hose, first_free_busno);
                /*
                 * Activate ULI1575 legacy chip by performing a fake
                 * memory access.  Needed to make ULI RTC work.
                 * Device 1d has the first on-board memory BAR.
                 */
-               pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
+               pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
                                PCI_BASE_ADDRESS_1, &temp32);
+
                if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-                       void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+                       void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
                                        temp32, 4, 0);
                        debug(" uli1572 read to %p\n", p);
                        in_be32(p);
                }
-       } else {
-               printf("PCIE3: disabled\n");
        }
-       puts("\n");
-#else
-       setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-       pcie_configured = is_serdes_configured(PCIE2);
-
-       if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
-               SET_STD_PCIE_INFO(pci_info[num], 2);
-               pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-               printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                                       &pcie2_hose, first_free_busno);
-       } else {
-               printf("PCIE2: disabled\n");
-       }
-
-       puts("\n");
-#else
-       setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-       pcie_configured = is_serdes_configured(PCIE1);
-
-       if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-               SET_STD_PCIE_INFO(pci_info[num], 1);
-               pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                                       &pcie1_hose, first_free_busno);
-       } else {
-               printf("PCIE1: disabled\n");
-       }
-
-       puts("\n");
-#else
-       setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
 }
 #endif
 

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 8cdcbea..9ec02cc 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -467,6 +467,7 @@
  */
 
 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_NAME          "ULI"
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
@@ -486,6 +487,7 @@
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME          "Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
@@ -505,6 +507,7 @@
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME          "Slot 2"
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000