} while (frag_offset < len);
- rtl92e_writeb(dev, TPPoll, TPPoll_CQ);
+ rtl92e_writeb(dev, TP_POLL, TPPoll_CQ);
Failed:
return rt_status;
}
_rtl92e_hwconfig(dev);
rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
- rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
- (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
+ rtl92e_writeb(dev, PCIF, ((MXDMA2_NO_LIMIT << MXDMA2_RX_SHIFT) |
+ (MXDMA2_NO_LIMIT << MXDMA2_TX_SHIFT)));
rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
rtl92e_writel(dev, RCR, priv->receive_config);
#define EEPROM_CID_Pronet 0x7
#define EEPROM_CID_DLINK 0x8
#define EEPROM_CID_WHQL 0xFE
-enum _RTL8192Pci_HW {
+enum _RTL8192PCI_HW {
MAC0 = 0x000,
MAC4 = 0x004,
PCIF = 0x009,
-#define MXDMA2_NoLimit 0x7
+#define MXDMA2_NO_LIMIT 0x7
#define MXDMA2_RX_SHIFT 4
#define MXDMA2_TX_SHIFT 0
#define IMR_VODOK BIT1
#define IMR_ROK BIT0
ISR = 0x0f8,
- TPPoll = 0x0fd,
+ TP_POLL = 0x0fd,
#define TPPoll_CQ BIT5
PSR = 0x0ff,
CPU_GEN = 0x100,
spin_unlock_irqrestore(&priv->irq_th_lock, flags);
netif_trans_update(dev);
- rtl92e_writew(dev, TPPoll, 0x01 << tcb_desc->queue_index);
+ rtl92e_writew(dev, TP_POLL, 0x01 << tcb_desc->queue_index);
return 0;
}