/// \brief Information about a load/store intrinsic defined by the target.
struct MemIntrinsicInfo {
- MemIntrinsicInfo()
- : ReadMem(false), WriteMem(false), IsSimple(false), MatchingId(0),
- NumMemRefs(0), PtrVal(nullptr) {}
- bool ReadMem;
- bool WriteMem;
- /// True only if this memory operation is non-volatile, non-atomic, and
- /// unordered. (See LoadInst/StoreInst for details on each)
- bool IsSimple;
- // Same Id is set by the target for corresponding load/store intrinsics.
- unsigned short MatchingId;
- int NumMemRefs;
-
/// This is the pointer that the intrinsic is loading from or storing to.
/// If this is non-null, then analysis/optimization passes can assume that
/// this intrinsic is functionally equivalent to a load/store from this
/// pointer.
- Value *PtrVal;
+ Value *PtrVal = nullptr;
+
+ // Ordering for atomic operations.
+ AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
+
+ // Same Id is set by the target for corresponding load/store intrinsics.
+ unsigned short MatchingId = 0;
+
+ bool ReadMem = false;
+ bool WriteMem = false;
+ bool IsVolatile = false;
+
+ bool isUnordered() const {
+ return (Ordering == AtomicOrdering::NotAtomic ||
+ Ordering == AtomicOrdering::Unordered) && !IsVolatile;
+ }
};
/// \brief This pass provides access to the codegen interfaces that are needed
case Intrinsic::aarch64_neon_ld4:
Info.ReadMem = true;
Info.WriteMem = false;
- Info.IsSimple = true;
- Info.NumMemRefs = 1;
Info.PtrVal = Inst->getArgOperand(0);
break;
case Intrinsic::aarch64_neon_st2:
case Intrinsic::aarch64_neon_st4:
Info.ReadMem = false;
Info.WriteMem = true;
- Info.IsSimple = true;
- Info.NumMemRefs = 1;
Info.PtrVal = Inst->getArgOperand(Inst->getNumArgOperands() - 1);
break;
}
ParseMemoryInst(Instruction *Inst, const TargetTransformInfo &TTI)
: IsTargetMemInst(false), Inst(Inst) {
if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst))
- if (TTI.getTgtMemIntrinsic(II, Info) && Info.NumMemRefs == 1)
+ if (TTI.getTgtMemIntrinsic(II, Info))
IsTargetMemInst = true;
}
bool isLoad() const {
return isa<StoreInst>(Inst);
}
bool isAtomic() const {
- if (IsTargetMemInst) {
- assert(Info.IsSimple && "need to refine IsSimple in TTI");
- return false;
- }
+ if (IsTargetMemInst)
+ return Info.Ordering != AtomicOrdering::NotAtomic;
return Inst->isAtomic();
}
bool isUnordered() const {
- if (IsTargetMemInst) {
- assert(Info.IsSimple && "need to refine IsSimple in TTI");
- return true;
- }
+ if (IsTargetMemInst)
+ return Info.isUnordered();
+
if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
return LI->isUnordered();
} else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
}
bool isVolatile() const {
- if (IsTargetMemInst) {
- assert(Info.IsSimple && "need to refine IsSimple in TTI");
- return false;
- }
+ if (IsTargetMemInst)
+ return Info.IsVolatile;
+
if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
return LI->isVolatile();
} else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) {