ARM i.MX53: mba53: fix lvds/disp pinctrl
authorSteffen Trumtrar <s.trumtrar@pengutronix.de>
Tue, 4 Jun 2013 11:07:14 +0000 (13:07 +0200)
committerShawn Guo <shawn.guo@linaro.org>
Mon, 17 Jun 2013 08:04:28 +0000 (16:04 +0800)
use NO_PAD_CTL / 0x80000000 instead of 0x10000 to prevent misconfigured pads

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
[Steffen: split up patch into tqma53+mba53 part]
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/imx53-mba53.dts

index 4515d01..869aa3e 100644 (file)
        lvds1 {
                pinctrl_lvds1_1: lvds1-grp1 {
                        fsl,pins = <
-                               MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
-                               MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
-                               MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
-                               MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
-                               MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
+                               MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
+                               MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
+                               MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
+                               MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
+                               MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
                        >;
                };
 
                pinctrl_lvds1_2: lvds1-grp2 {
                        fsl,pins = <
-                               MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
-                               MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
-                               MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
-                               MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
-                               MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
+                               MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
+                               MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
+                               MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
+                               MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
+                               MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
                        >;
                };
        };
        disp1 {
                pinctrl_disp1_1: disp1-grp1 {
                        fsl,pins = <
-                               MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
-                               MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
-                               MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
-                               MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
-                               MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
-                               MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
-                               MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
-                               MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
-                               MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
-                               MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
-                               MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
-                               MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
-                               MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
-                               MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
-                               MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
-                               MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
-                               MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
-                               MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
-                               MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
-                               MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
-                               MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
-                               MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
-                               MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
-                               MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
-                               MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
-                               MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
-                               MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
+                               MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
+                               MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
+                               MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
+                               MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
+                               MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
+                               MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
+                               MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
+                               MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
+                               MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
+                               MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
+                               MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
+                               MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
+                               MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
+                               MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
+                               MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
+                               MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
+                               MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
+                               MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
+                               MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
+                               MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
+                               MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
+                               MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
+                               MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
+                               MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
+                               MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
+                               MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
+                               MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
                        >;
                };
        };