radeon: make PCI GART aperture size variable, but making table size variable

This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0

diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 976b9fb..e02796e 100644 (file)
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1622,9 +1622,8 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
        } else
 #endif
        {
-               dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
                /* if we have an offset set from userspace */
-               if (dev_priv->pcigart_offset) {
+               if (dev_priv->pcigart_offset_set) {
                        dev_priv->gart_info.bus_addr =
                            dev_priv->pcigart_offset + dev_priv->fb_location;
                        dev_priv->gart_info.mapping.offset =
@@ -2231,6 +2230,8 @@ int radeon_driver_firstopen(struct drm_device *dev)
        drm_local_map_t *map;
        drm_radeon_private_t *dev_priv = dev->dev_private;
 
+       dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
+
        ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
                         drm_get_resource_len(dev, 2), _DRM_REGISTERS,
                         _DRM_READ_ONLY, &dev_priv->mmio);

diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
index f5edbc1..e96e785 100644 (file)
--- a/shared-core/radeon_drm.h
+++ b/shared-core/radeon_drm.h
@@ -708,6 +708,7 @@ typedef struct drm_radeon_setparam {
 #define RADEON_SETPARAM_PCIGART_LOCATION 3     /* PCI Gart Location */
 
 #define RADEON_SETPARAM_NEW_MEMMAP 4           /* Use new memory map */
+#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 
 /* 1.14: Clients can allocate/free a surface
  */

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 5c426fe..3e56af3 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -95,10 +95,11 @@
  * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
  * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
  *       new packet type)
+ * 1.26- Add support for variable size PCI(E) gart aperture
  */
 
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           25
+#define DRIVER_MINOR           26
 #define DRIVER_PATCHLEVEL      0
 
 /*
@@ -282,6 +283,7 @@ typedef struct drm_radeon_private {
        struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
 
        unsigned long pcigart_offset;
+       unsigned int pcigart_offset_set;
        drm_ati_pcigart_info gart_info;
 
        u32 scratch_ages[5];

diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 40b7d6c..b95549d 100644 (file)
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -3196,10 +3196,16 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
                break;
        case RADEON_SETPARAM_PCIGART_LOCATION:
                dev_priv->pcigart_offset = sp.value;
+               dev_priv->pcigart_offset_set = 1;
                break;
        case RADEON_SETPARAM_NEW_MEMMAP:
                dev_priv->new_memmap = sp.value;
                break;
+       case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
+               dev_priv->gart_info.table_size = sp.value;
+               if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
+                       dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
+               break;
        default:
                DRM_DEBUG("Invalid parameter %d\n", sp.param);
                return DRM_ERR(EINVAL);