unsigned VecTySize = thisT()->getDataLayout().getTypeStoreSize(VecTy);
unsigned VecTyLTSize = VecTyLT.getStoreSize();
- // Return the ceiling of dividing A by B.
- auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
-
// Scale the cost of the memory operation by the fraction of legalized
// instructions that will actually be used. We shouldn't account for the
// cost of dead instructions since they will be removed.
if (Opcode == Instruction::Load && VecTySize > VecTyLTSize) {
// The number of loads of a legal type it will take to represent a load
// of the unlegalized vector type.
- unsigned NumLegalInsts = ceil(VecTySize, VecTyLTSize);
+ unsigned NumLegalInsts = divideCeil(VecTySize, VecTyLTSize);
// The number of elements of the unlegalized type that correspond to a
// single legal instruction.
- unsigned NumEltsPerLegalInst = ceil(NumElts, NumLegalInsts);
+ unsigned NumEltsPerLegalInst = divideCeil(NumElts, NumLegalInsts);
// Determine which legal instructions will be used.
BitVector UsedInsts(NumLegalInsts, false);
assert(isa<VectorType>(VecTy) &&
"Expect a vector type for interleaved memory op");
- // Return the ceiling of dividing A by B.
- auto ceil = [](unsigned A, unsigned B) { return (A + B - 1) / B; };
-
unsigned NumElts = cast<FixedVectorType>(VecTy)->getNumElements();
assert(Factor > 1 && NumElts % Factor == 0 && "Invalid interleave factor");
unsigned VF = NumElts / Factor;
// requires one operation, except that vperm can handle two input
// registers first time for each dst vector.
unsigned NumSrcVecs = ValueVecs[Index].count();
- unsigned NumDstVecs = ceil(VF * getScalarSizeInBits(VecTy), 128U);
+ unsigned NumDstVecs = divideCeil(VF * getScalarSizeInBits(VecTy), 128U);
assert (NumSrcVecs >= NumDstVecs && "Expected at least as many sources");
NumPermutes += std::max(1U, NumSrcVecs - NumDstVecs);
}