* sparc-opc.c (architecture_pname): Add v9a.

The actual insns haven't been added yet.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d8ca155..e03f342 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Mon Jan 22 08:29:59 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+       * sparc-opc.c (architecture_pname): Add v9a.
+
 Fri Jan 12 14:35:58 1996  David Mosberger-Tang  <davidm@AZStarNet.com>
 
        * alpha-opc.h (alpha_insn_set): VAX floating point opcode was

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 063ec6b..3dde31b 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1,5 +1,5 @@
 /* Table of opcodes for the sparc.
-   Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc.
+   Copyright (C) 1989, 1991, 1992, 1995, 1996 Free Software Foundation, Inc.
 
 This file is part of the BFD library.
 
@@ -22,8 +22,7 @@ Boston, MA 02111-1307, USA.   */
    instruction's name rather than the args.  This would make gas faster, pinsn
    slower, but would mess up some macros a bit.  xoxorich. */
 
-/* v9 FIXME: Doesn't accept `iprefetch', `setX', `signx', `cleartop', `cas',
-   `casx', `clrx', `clruw' synthetic instructions for v9.  */
+/* v9 FIXME: Doesn't accept `setsw', `setx' synthetic instructions for v9.  */
 
 #include <stdio.h>
 #include "ansidecl.h"
@@ -35,11 +34,10 @@ const char *architecture_pname[] = {
        "v8",
        "sparclite",
        "v9",
+       "v9a", /* v9 with ultrasparc additions */
        NULL,
 };
 
-/* v9: This file is correct for SPARC Version 9 Draft 1.2.4.  */
-
 /* Branch condition field.  */
 #define COND(x)                (((x)&0xf)<<25)
 
@@ -448,14 +446,14 @@ struct sparc_opcode sparc_opcodes[] = {
 { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[1+i]", 0, v6 },
 { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1),              "d,[i+1]", 0, v6 },
 { "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,       "d,[i]", 0, v6 },
-{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* sth d,[+] */
+{ "sth",       F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),   "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
 
 { "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0),              "d,[1+2]A", 0, v6 },
-{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stha ,[+%] */
+{ "stha",      F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),      "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
 { "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[1+i]o", 0, v9 },
 { "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1),              "d,[i+1]o", 0, v9 },
 { "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
-{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* sth d,[+] */
+{ "stha",      F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
 
 { "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),      "d,[1+2]", 0, v9 },
 { "stx",       F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),  "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
@@ -465,32 +463,32 @@ struct sparc_opcode sparc_opcodes[] = {
 { "stx",       F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),   "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
 
 { "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
-{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* st d,[rs1+%g0] */
+{ "stx",       F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
 { "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[1+i]", 0, v9 },
 { "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),         "F,[i+1]", 0, v9 },
 { "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),  "F,[i]", 0, v9 },
-{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* st d,[rs1+0] */
+{ "stx",       F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
 
 { "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),              "d,[1+2]A", 0, v9 },
-{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),      "d,[1]A", 0, v9 }, /* stha d,[rs1+%g0] */
+{ "stxa",      F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),      "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
 { "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[1+i]o", 0, v9 },
 { "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),              "d,[i+1]o", 0, v9 },
 { "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,       "d,[i]o", 0, v9 },
 { "stxa",      F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),   "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
 
 { "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),      "J,[1+2]", 0, v9 },
-{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, v9 }, /* st d[rs1+%g0] */
+{ "stq",       F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),  "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
 { "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[1+i]", 0, v9 },
 { "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1),              "J,[i+1]", 0, v9 },
 { "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,       "J,[i]", 0, v9 },
-{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "J,[1]", 0, v9 }, /* st d,[rs1+0] */
+{ "stq",       F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),   "J,[1]", 0, v9 }, /* stq [rs1+0] */
 
 { "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),      "J,[1+2]A", 0, v9 },
-{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, v9 }, /* st d[rs1+%g0] */
+{ "stqa",      F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),  "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
 { "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[1+i]o", 0, v9 },
 { "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1),              "J,[i+1]o", 0, v9 },
 { "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,       "J,[i]o", 0, v9 },
-{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "J,[1]o", 0, v9 }, /* st d,[rs1+0] */
+{ "stqa",      F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),   "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
 
 { "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),      "[1+2],d", 0, v7 },
 { "swap",      F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),  "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
@@ -513,15 +511,15 @@ struct sparc_opcode sparc_opcodes[] = {
 
 { "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
 { "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1,%g0 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,        "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,        "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,"i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 },    /* rett X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, v6 },    /* rett X */
 { "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, v6 },    /* rett rs1+0 */
 
 { "save",      F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 { "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, v6 },
-{ "save",      0x81e00000,     ~0x81e00000,    "", F_ALIAS, v6 },
+{ "save",      0x81e00000,     ~0x81e00000,                    "", F_ALIAS, v6 },
 
 { "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),           "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
@@ -614,22 +612,29 @@ struct sparc_opcode sparc_opcodes[] = {
 { "clr",       F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),            "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
 { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[1+i]", F_ALIAS, v6 },
 { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,                        "[i+1]", F_ALIAS, v6 },
-{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
+{ "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,                 "[i]", F_ALIAS, v6 },
 { "clr",       F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),             "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
 
 { "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
 { "clrb",      F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
 { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
 { "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
-{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* clrb [rs1+0],d */
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
+{ "clrb",      F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
 
 { "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v6 },
 { "clrh",      F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
 { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[1+i]", F_ALIAS, v6 },
 { "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,                "[i+1]", F_ALIAS, v6 },
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
-{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* clrb [rs1+0],d */
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v6 },
+{ "clrh",      F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
+
+{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),        "[1+2]", F_ALIAS, v9 },
+{ "clrx",      F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),    "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[1+i]", F_ALIAS, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,                "[i+1]", F_ALIAS, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,         "[i]", F_ALIAS, v9 },
+{ "clrx",      F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),     "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
 
 { "orcc",      F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),      "1,2,d", 0, v6 },
 { "orcc",      F3(2, 0x12, 1), F3(~2, ~0x12, ~1),              "1,i,d", 0, v6 },
@@ -658,14 +663,12 @@ struct sparc_opcode sparc_opcodes[] = {
 { "wr",        F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_NOTV9, v6 }, /* wr r,r,%tbr */
 { "wr",        F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_NOTV9, v6 }, /* wr r,i,%tbr */
 
-{ "wr", F3(2, 0x30, 0)|RD(0), F3(~2, ~0x30, ~0)|RD(~0)|ASI(~0), "1,2,y", 0, v9 }, /* wr r,r,%y */
-{ "wr", F3(2, 0x30, 1)|RD(0), F3(~2, ~0x30, ~1)|RD(~0),                "1,i,y", 0, v9 }, /* wr r,i,%y */
-{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
-{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2),                "1,i,E", 0, v9 }, /* wr r,i,%ccr */
-{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
-{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3),                "1,i,o", 0, v9 }, /* wr r,i,%asi */
-{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,i,%fprs */
-{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6),                "1,i,s", 0, v9 }, /* wr r,i,%fprs */
+{ "wr", F3(2, 0x30, 0)|RD(2),  F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),       "1,2,E", 0, v9 }, /* wr r,r,%ccr */
+{ "wr", F3(2, 0x30, 1)|RD(2),  F3(~2, ~0x30, ~1)|RD(~2),               "1,i,E", 0, v9 }, /* wr r,i,%ccr */
+{ "wr", F3(2, 0x30, 0)|RD(3),  F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),       "1,2,o", 0, v9 }, /* wr r,r,%asi */
+{ "wr", F3(2, 0x30, 1)|RD(3),  F3(~2, ~0x30, ~1)|RD(~3),               "1,i,o", 0, v9 }, /* wr r,i,%asi */
+{ "wr", F3(2, 0x30, 0)|RD(6),  F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),       "1,2,s", 0, v9 }, /* wr r,i,%fprs */
+{ "wr", F3(2, 0x30, 1)|RD(6),  F3(~2, ~0x30, ~1)|RD(~6),               "1,i,s", 0, v9 }, /* wr r,i,%fprs */
 
 { "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|SIMM13(~0),           "M,d", 0, v8 }, /* rd %asrX,r */
 { "rd",        F3(2, 0x28, 0),                 F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),    "y,d", 0, v6 }, /* rd %y,r */
@@ -690,31 +693,31 @@ struct sparc_opcode sparc_opcodes[] = {
 { "mov",       F3(2, 0x30, 0),         F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),        "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
 { "mov",       F3(2, 0x30, 1),         F3(~2, ~0x30, ~1),                      "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
 { "mov",       F3(2, 0x30, 1),         F3(~2, ~0x30, ~1)|RD_G0,                "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
-{ "mov",       F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS, v6 }, /* wr r,r,%psr */
-{ "mov",       F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS, v6 }, /* wr r,i,%psr */
-{ "mov",       F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS, v6 }, /* wr r,r,%wim */
-{ "mov",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS, v6 }, /* wr r,i,%wim */
-{ "mov",       F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS, v6 }, /* wr r,r,%tbr */
-{ "mov",       F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS, v6 }, /* wr r,i,%tbr */
-
-{ "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|SIMM13(~0),                  "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
-{ "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),           "y,d", F_ALIAS, v6 }, /* rd %y,r */
-{ "mov",       F3(2, 0x29, 0),          F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),           "p,d", F_ALIAS|F_NOTV9, v6 }, /* rd %psr,r */
-{ "mov",       F3(2, 0x2a, 0),          F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),           "w,d", F_ALIAS|F_NOTV9, v6 }, /* rd %wim,r */
-{ "mov",       F3(2, 0x2b, 0),          F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),           "t,d", F_ALIAS|F_NOTV9, v6 }, /* rd %tbr,r */
+{ "mov",       F3(2, 0x31, 0),         F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),        "1,2,p", F_ALIAS|F_NOTV9, v6 }, /* wr r,r,%psr */
+{ "mov",       F3(2, 0x31, 1),         F3(~2, ~0x31, ~1)|RD_G0,                "1,i,p", F_ALIAS|F_NOTV9, v6 }, /* wr r,i,%psr */
+{ "mov",       F3(2, 0x32, 0),         F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),        "1,2,w", F_ALIAS|F_NOTV9, v6 }, /* wr r,r,%wim */
+{ "mov",       F3(2, 0x32, 1),         F3(~2, ~0x32, ~1)|RD_G0,                "1,i,w", F_ALIAS|F_NOTV9, v6 }, /* wr r,i,%wim */
+{ "mov",       F3(2, 0x33, 0),         F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),        "1,2,t", F_ALIAS|F_NOTV9, v6 }, /* wr r,r,%tbr */
+{ "mov",       F3(2, 0x33, 1),         F3(~2, ~0x33, ~1)|RD_G0,                "1,i,t", F_ALIAS|F_NOTV9, v6 }, /* wr r,i,%tbr */
+
+{ "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|SIMM13(~0),          "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
+{ "mov",       F3(2, 0x28, 0),          F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),   "y,d", F_ALIAS, v6 }, /* rd %y,r */
+{ "mov",       F3(2, 0x29, 0),          F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),   "p,d", F_ALIAS|F_NOTV9, v6 }, /* rd %psr,r */
+{ "mov",       F3(2, 0x2a, 0),          F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),   "w,d", F_ALIAS|F_NOTV9, v6 }, /* rd %wim,r */
+{ "mov",       F3(2, 0x2b, 0),          F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),   "t,d", F_ALIAS|F_NOTV9, v6 }, /* rd %tbr,r */
 
 { "mov",       F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),  "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
 { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1),              "i,y", F_ALIAS, v6 },
 { "mov",       F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),   "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
-{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0),  "1,p", F_ALIAS, v6 }, /* wr rs1,%g0,%psr */
-{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1),              "i,p", F_ALIAS, v6 },
-{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0),   "1,p", F_ALIAS, v6 }, /* wr rs1,0,%psr */
-{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0),  "1,w", F_ALIAS, v6 }, /* wr rs1,%g0,%wim */
-{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1),              "i,w", F_ALIAS, v6 },
-{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0),   "1,w", F_ALIAS, v6 }, /* wr rs1,0,%wim */
-{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0),  "1,t", F_ALIAS, v6 }, /* wr rs1,%g0,%tbr */
-{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1),              "i,t", F_ALIAS, v6 },
-{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0),   "1,t", F_ALIAS, v6 }, /* wr rs1,0,%tbr */
+{ "mov",       F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|ASI_RS2(~0),  "1,p", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,%g0,%psr */
+{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1),              "i,p", F_ALIAS|F_NOTV9, v6 },
+{ "mov",       F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|SIMM13(~0),   "1,p", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,0,%psr */
+{ "mov",       F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|ASI_RS2(~0),  "1,w", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,%g0,%wim */
+{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1),              "i,w", F_ALIAS|F_NOTV9, v6 },
+{ "mov",       F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|SIMM13(~0),   "1,w", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,0,%wim */
+{ "mov",       F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|ASI_RS2(~0),  "1,t", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,%g0,%tbr */
+{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1),              "i,t", F_ALIAS|F_NOTV9, v6 },
+{ "mov",       F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|SIMM13(~0),   "1,t", F_ALIAS|F_NOTV9, v6 }, /* wr rs1,0,%tbr */
 
 { "mov",       F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),       "2,d", 0, v6 }, /* or %g0,rs2,d */
 { "mov",       F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,               "i,d", 0, v6 }, /* or %g0,i,d   */
@@ -1447,6 +1450,16 @@ IMPDEP ("impdep2", 0x37),
 { "casxa",     F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
 { "casxa",     F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
 
+/* v9 synthetic insns */
+/* FIXME: still missing "signx d", and "clruw d".  Can't be done here.  */
+{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
+{ "signx",     F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
+{ "clruw",     F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
+{ "cas",       F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
+{ "casl",      F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
+{ "casx",      F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
+{ "casxl",     F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
+
 };
 
 const int bfd_sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));