.init_machine = omap_2430sdp_init,
.init_late = omap2430_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
.init_machine = omap_3430sdp_init,
.init_late = omap3430_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap_sdp_init,
.init_late = omap3630_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap_4430sdp_init,
.init_late = omap4430_init_late,
.timer = &omap4_timer,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
.init_machine = am3517_crane_init,
.init_late = am35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = am3517_evm_init,
.init_late = am35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap_apollon_init,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
.init_machine = cm_t35_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(CM_T3730, "Compulab CM-T3730")
- .atag_offset = 0x100,
- .reserve = omap_reserve,
- .map_io = omap3_map_io,
- .init_early = omap3630_init_early,
- .init_irq = omap3_init_irq,
+ .atag_offset = 0x100,
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = omap3630_init_early,
+ .init_irq = omap3_init_irq,
.handle_irq = omap3_intc_handle_irq,
- .init_machine = cm_t3730_init,
+ .init_machine = cm_t3730_init,
.init_late = omap3630_init_late,
- .timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .timer = &omap3_timer,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = cm_t3517_init,
.init_late = am35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = devkit8000_init,
.init_late = omap35xx_init_late,
.timer = &omap3_secure_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap_generic_init,
.timer = &omap2_timer,
.dt_compat = omap242x_boards_compat,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
#endif
.init_machine = omap_generic_init,
.timer = &omap2_timer,
.dt_compat = omap243x_boards_compat,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
#endif
.init_machine = omap_generic_init,
.timer = &omap3_timer,
.dt_compat = omap3_boards_compat,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
#endif
.init_late = omap4430_init_late,
.timer = &omap4_timer,
.dt_compat = omap4_boards_compat,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
#endif
.init_machine = omap_generic_init,
.timer = &omap5_timer,
.dt_compat = omap5_boards_compat,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
#endif
.init_machine = omap_h4_init,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
.init_machine = igep_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.init_machine = igep_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap_ldp_init,
.init_late = omap3430_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.init_machine = n8x0_init_machine,
.init_late = omap2420_init_late,
.timer = &omap2_timer,
- .restart = omap_prcm_restart,
+ .restart = omap2xxx_restart,
MACHINE_END
.init_machine = omap3_beagle_init,
.init_late = omap3_init_late,
.timer = &omap3_secure_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap3_evm_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.init_machine = omap3logic_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap3pandora_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap3_stalker_init,
.init_late = omap35xx_init_late,
.timer = &omap3_secure_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap3_touchbook_init,
.init_late = omap3430_init_late,
.timer = &omap3_secure_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = omap4_panda_init,
.init_late = omap4430_init_late,
.timer = &omap4_timer,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
.init_machine = overo_init,
.init_late = omap35xx_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = rm680_init,
.init_late = omap3630_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
.init_machine = rm680_init,
.init_late = omap3630_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.init_machine = rx51_init,
.init_late = omap3430_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
.timer = &omap3_timer,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
MACHINE_START(TI8148EVM, "ti8148evm")
.timer = &omap3_timer,
.init_machine = ti81xx_evm_init,
.init_late = ti81xx_init_late,
- .restart = omap_prcm_restart,
+ .restart = omap44xx_restart,
MACHINE_END
.init_machine = omap_zoom_init,
.init_late = omap3430_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.init_machine = omap_zoom_init,
.init_late = omap3630_init_late,
.timer = &omap3_timer,
- .restart = omap_prcm_restart,
+ .restart = omap3xxx_restart,
MACHINE_END
u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
-int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
-
-
-#ifdef CONFIG_ARCH_OMAP2
-void omap2xxx_clk_prepare_for_reboot(void);
-#else
-static inline void omap2xxx_clk_prepare_for_reboot(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap3_clk_prepare_for_reboot(void);
-#else
-static inline void omap3_clk_prepare_for_reboot(void)
-{
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-void omap4_clk_prepare_for_reboot(void);
-#else
-static inline void omap4_clk_prepare_for_reboot(void)
-{
-}
-#endif
-
int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
extern const struct clkops clkops_omap2_dflt;
extern struct clk_functions omap2_clk_functions;
-extern struct clk *vclk, *sclk;
extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
*/
clk_enable_init_clocks();
- /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
- vclk = clk_get(NULL, "virt_prcm_set");
- sclk = clk_get(NULL, "sys_ck");
-
return 0;
}
*/
clk_enable_init_clocks();
- /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
- vclk = clk_get(NULL, "virt_prcm_set");
- sclk = clk_get(NULL, "sys_ck");
-
return 0;
}
#include "cm.h"
#include "cm-regbits-24xx.h"
-struct clk *vclk, *sclk;
-
/*
* Omap24xx specific clock functions
*/
/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2xxx_clk_prepare_for_reboot(void)
-{
- u32 rate;
-
- if (vclk == NULL || sclk == NULL)
- return;
-
- rate = clk_get_rate(sclk);
- clk_set_rate(vclk, rate);
-}
-
-/*
* Switch the MPU rate if specified on cmdline. We cannot do this
* early until cmdline is parsed. XXX This should be removed from the
* clock code and handled by the OPP layer code in the near future.
void ti81xx_init_late(void);
void omap4430_init_late(void);
int omap2_common_pm_late_init(void);
-void omap_prcm_restart(char, const char *);
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
void omap2xxx_restart(char mode, const char *cmd);
#define MAX_MODULE_ENABLE_WAIT 100000
-/* Resets clock rates and reboots the system. Only called from system.h */
-void omap_prcm_restart(char mode, const char *cmd)
-{
- s16 prcm_offs = 0;
-
- if (cpu_is_omap24xx()) {
- omap2xxx_clk_prepare_for_reboot();
-
- prcm_offs = WKUP_MOD;
- } else if (cpu_is_omap34xx()) {
- prcm_offs = OMAP3430_GR_MOD;
- omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
- } else if (cpu_is_omap44xx()) {
- omap4_prminst_global_warm_sw_reset(); /* never returns */
- } else {
- WARN_ON(1);
- }
-
- /*
- * As per Errata i520, in some cases, user will not be able to
- * access DDR memory after warm-reset.
- * This situation occurs while the warm-reset happens during a read
- * access to DDR memory. In that particular condition, DDR memory
- * does not respond to a corrupted read command due to the warm
- * reset occurrence but SDRC is waiting for read completion.
- * SDRC is not sensitive to the warm reset, but the interconnect is
- * reset on the fly, thus causing a misalignment between SDRC logic,
- * interconnect logic and DDR memory state.
- * WORKAROUND:
- * Steps to perform before a Warm reset is trigged:
- * 1. enable self-refresh on idle request
- * 2. put SDRC in idle
- * 3. wait until SDRC goes to idle
- * 4. generate SW reset (Global SW reset)
- *
- * Steps to be performed after warm reset occurs (in bootloader):
- * if HW warm reset is the source, apply below steps before any
- * accesses to SDRAM:
- * 1. Reset SMS and SDRC and wait till reset is complete
- * 2. Re-initialize SMS, SDRC and memory
- *
- * NOTE: Above work around is required only if arch reset is implemented
- * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
- * the WA since it resets SDRC as well as part of cold reset.
- */
-
- /* XXX should be moved to some OMAP2/3 specific code */
- omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
- OMAP2_RM_RSTCTRL);
- omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
-}
-
/**
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
* @reg: physical address of module IDLEST register
projects / profile / ivi / kernel-x86-ivi.git / commitdiff