arm64: dts: qcom: sm8350-hdk: enable PCIe devices

Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-9-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 26a6081..c638c70 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -230,6 +230,39 @@
        firmware-name = "qcom/sm8350/modem.mbn";
 };
 
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_default_state>;
+
+       perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+       status = "okay";
+};
+
+&pcie0_phy {
+       vdda-phy-supply = <&vreg_l5b_0p88>;
+       vdda-pll-supply = <&vreg_l6b_1p2>;
+
+       status = "okay";
+};
+
+&pcie1 {
+       perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_default_state>;
+
+       status = "okay";
+};
+
+&pcie1_phy {
+       status = "okay";
+       vdda-phy-supply = <&vreg_l5b_0p88>;
+       vdda-pll-supply = <&vreg_l6b_1p2>;
+};
+
 &qupv3_id_0 {
        status = "okay";
 };
@@ -241,6 +274,53 @@
 
 &tlmm {
        gpio-reserved-ranges = <52 8>;
+
+       pcie0_default_state: pcie0-default-state {
+               perst-pins {
+                       pins = "gpio94";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               clkreq-pins {
+                       pins = "gpio95";
+                       function = "pcie0_clkreqn";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               wake-pins {
+                       pins = "gpio96";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie1_default_state: pcie1-default-state {
+               perst-pins {
+                       pins = "gpio97";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+
+               clkreq-pins {
+                       pins = "gpio98";
+                       function = "pcie1_clkreqn";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               wake-pins {
+                       pins = "gpio99";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
 };
 
 &uart2 {