drm/i915: Clean up GAMMA_MODE defines

Use REG_BIT() & co. for GAMMA_MODE bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123152638.20622-3-ville.syrjala@linux.intel.com
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab39cfb..6c91e42 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5308,14 +5308,14 @@
 #define _GAMMA_MODE_A          0x4a480
 #define _GAMMA_MODE_B          0x4ac80
 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
-#define  PRE_CSC_GAMMA_ENABLE  (1 << 31)
-#define  POST_CSC_GAMMA_ENABLE (1 << 30)
-#define  GAMMA_MODE_MODE_MASK  (3 << 0)
-#define  GAMMA_MODE_MODE_8BIT  (0 << 0)
-#define  GAMMA_MODE_MODE_10BIT (1 << 0)
-#define  GAMMA_MODE_MODE_12BIT (2 << 0)
-#define  GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
-#define  GAMMA_MODE_MODE_12BIT_MULTI_SEG       (3 << 0) /* icl-tgl */
+#define  PRE_CSC_GAMMA_ENABLE                  REG_BIT(31) /* icl+ */
+#define  POST_CSC_GAMMA_ENABLE                 REG_BIT(30) /* icl+ */
+#define  GAMMA_MODE_MODE_MASK                  REG_GENMASK(1, 0)
+#define  GAMMA_MODE_MODE_8BIT                  REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
+#define  GAMMA_MODE_MODE_10BIT                 REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 1)
+#define  GAMMA_MODE_MODE_12BIT                 REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 2)
+#define  GAMMA_MODE_MODE_SPLIT                 REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
+#define  GAMMA_MODE_MODE_12BIT_MULTI_SEG       REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
 
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT             _MMIO(0x42060)