pTxFwInfo->TxSubCarrier = 0;
} else {
pTxFwInfo->TxBandwidth = 0;
- pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
+ pTxFwInfo->TxSubCarrier = priv->n_cur_40mhz_prime_sc;
}
} else {
pTxFwInfo->TxBandwidth = 0;
}
rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
- (priv->nCur40MhzPrimeSC>>1));
+ (priv->n_cur_40mhz_prime_sc>>1));
rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
- priv->nCur40MhzPrimeSC);
+ priv->n_cur_40mhz_prime_sc);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
break;
priv->CurrentChannelBW = bandwidth;
if (Offset == HT_EXTCHNL_OFFSET_LOWER)
- priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
+ priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_UPPER;
else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
- priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
+ priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_LOWER;
else
- priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
_rtl92e_set_bw_mode_work_item(dev);
goto END;
}
priv->rf_change_in_progress = true;
- priv->bResetInProgress = true;
+ priv->reset_in_progress = true;
spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
RESET_START:
END:
priv->rst_progress = RESET_TYPE_NORESET;
priv->reset_count++;
- priv->bResetInProgress = false;
+ priv->reset_in_progress = false;
rtl92e_writeb(dev, UFWP, 1);
}
if ((priv->force_reset || ResetType == RESET_TYPE_SILENT))
_rtl92e_if_silent_reset(dev);
priv->force_reset = false;
- priv->bResetInProgress = false;
+ priv->reset_in_progress = false;
}
static void _rtl92e_watchdog_timer_cb(struct timer_list *t)
u8 queue_index = tcb_desc->queue_index;
if ((priv->rtllib->rf_power_state == rf_off) || !priv->up ||
- priv->bResetInProgress) {
+ priv->reset_in_progress) {
kfree_skb(skb);
return;
}
if (queue_index != TXCMD_QUEUE) {
if ((priv->rtllib->rf_power_state == rf_off) ||
- !priv->up || priv->bResetInProgress) {
+ !priv->up || priv->reset_in_progress) {
kfree_skb(skb);
return 0;
}
u8 SwChnlStep;
u8 SetBWModeInProgress;
- u8 nCur40MhzPrimeSC;
+ u8 n_cur_40mhz_prime_sc;
u32 rf_reg_0value[4];
u8 num_total_rf_path;
bool bswitch_fsync;
u8 framesync;
u32 framesyncC34;
- u8 framesyncMonitor;
+ u8 frame_sync_monitor;
u32 reset_count;
enum reset_type rst_progress;
u16 tx_counter;
u16 rx_ctr;
- bool bResetInProgress;
+ bool reset_in_progress;
bool force_reset;
bool force_lps;
if (Pwr_Flag == 0) {
mdelay(1);
- if (priv->bResetInProgress) {
+ if (priv->reset_in_progress) {
rtl92e_writeb(dev, Pw_Track_Flag, 0);
rtl92e_writeb(dev, FW_Busy_Flag, 0);
return;
priv->rtllib->fsync_firstdiff_ratethreshold = 100;
priv->rtllib->fsync_seconddiff_ratethreshold = 200;
priv->rtllib->fsync_state = Default_Fsync;
- priv->framesyncMonitor = 1;
+ priv->frame_sync_monitor = 1;
timer_setup(&priv->fsync_timer, _rtl92e_dm_fsync_timer_callback, 0);
}
}
}
- if (priv->framesyncMonitor) {
+ if (priv->frame_sync_monitor) {
if (reg_c38_State != RegC38_Fsync_AP_BCM) {
rtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95);
break;
}
- if (priv->framesyncMonitor) {
+ if (priv->frame_sync_monitor) {
if (priv->rtllib->state == RTLLIB_LINKED) {
if (priv->undecorated_smoothed_pwdb <=
RegC38_TH) {
}
}
}
- if (priv->framesyncMonitor) {
+ if (priv->frame_sync_monitor) {
if (priv->reset_count != reset_cnt) {
rtl92e_writeb(dev, rOFDM0_RxDetector3,
priv->framesync);