ath10k: fix shadow register implementation for WCN3990
authorRakesh Pillai <pillair@codeaurora.org>
Fri, 8 Feb 2019 13:50:24 +0000 (15:50 +0200)
committerKalle Valo <kvalo@codeaurora.org>
Mon, 11 Feb 2019 16:35:03 +0000 (18:35 +0200)
WCN3990 supports shadow registers write operation support
for copy engine for regular operation in powersave mode.

Since WCN3990 is a 64-bit target, the shadow register
implementation needs to be done in the copy engine handlers
for 64-bit target. Currently the shadow register implementation
is present in the 32-bit target handlers of copy engine.

Fix the shadow register copy engine write operation
implementation for 64-bit target(WCN3990).

Tested HW: WCN3990
Tested FW: WLAN.HL.2.0-01188-QCAHLSWMTPLZ-1

Fixes: b7ba83f7c414 ("ath10k: add support for shadow register for WNC3990")
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/ath/ath10k/ce.c
drivers/net/wireless/ath/ath10k/ce.h

index 8b4a910..32f4802 100644 (file)
@@ -545,14 +545,8 @@ static int _ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
        write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
 
        /* WORKAROUND */
-       if (!(flags & CE_SEND_FLAG_GATHER)) {
-               if (ar->hw_params.shadow_reg_support)
-                       ath10k_ce_shadow_src_ring_write_index_set(ar, ce_state,
-                                                                 write_index);
-               else
-                       ath10k_ce_src_ring_write_index_set(ar, ctrl_addr,
-                                                          write_index);
-       }
+       if (!(flags & CE_SEND_FLAG_GATHER))
+               ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
 
        src_ring->write_index = write_index;
 exit:
@@ -626,8 +620,14 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe *ce_state,
        /* Update Source Ring Write Index */
        write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
 
-       if (!(flags & CE_SEND_FLAG_GATHER))
-               ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
+       if (!(flags & CE_SEND_FLAG_GATHER)) {
+               if (ar->hw_params.shadow_reg_support)
+                       ath10k_ce_shadow_src_ring_write_index_set(ar, ce_state,
+                                                                 write_index);
+               else
+                       ath10k_ce_src_ring_write_index_set(ar, ctrl_addr,
+                                                          write_index);
+       }
 
        src_ring->write_index = write_index;
 exit:
@@ -1449,12 +1449,12 @@ static int ath10k_ce_alloc_shadow_base(struct ath10k *ar,
                                       u32 nentries)
 {
        src_ring->shadow_base_unaligned = kcalloc(nentries,
-                                                 sizeof(struct ce_desc),
+                                                 sizeof(struct ce_desc_64),
                                                  GFP_KERNEL);
        if (!src_ring->shadow_base_unaligned)
                return -ENOMEM;
 
-       src_ring->shadow_base = (struct ce_desc *)
+       src_ring->shadow_base = (struct ce_desc_64 *)
                        PTR_ALIGN(src_ring->shadow_base_unaligned,
                                  CE_DESC_RING_ALIGN);
        return 0;
@@ -1506,7 +1506,7 @@ ath10k_ce_alloc_src_ring(struct ath10k *ar, unsigned int ce_id,
                ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries);
                if (ret) {
                        dma_free_coherent(ar->dev,
-                                         (nentries * sizeof(struct ce_desc) +
+                                         (nentries * sizeof(struct ce_desc_64) +
                                           CE_DESC_RING_ALIGN),
                                          src_ring->base_addr_owner_space_unaligned,
                                          base_addr);
index c44a52e..f3b4f7e 100644 (file)
@@ -118,7 +118,7 @@ struct ath10k_ce_ring {
        dma_addr_t base_addr_ce_space;
 
        char *shadow_base_unaligned;
-       struct ce_desc *shadow_base;
+       struct ce_desc_64 *shadow_base;
 
        /* keep last */
        void *per_transfer_context[0];