drm/i915/edp: use MSO pixel overlap from DisplayID data
authorJani Nikula <jani.nikula@intel.com>
Tue, 31 Aug 2021 14:17:35 +0000 (17:17 +0300)
committerJani Nikula <jani.nikula@intel.com>
Tue, 14 Sep 2021 11:22:17 +0000 (14:22 +0300)
Now that we have MSO pixel overlap in display info, use it.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87d8d80ba205eb2ecb50f613219e0a821a842616.1630419362.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_dp.c

index 9015ed7..2db606a 100644 (file)
@@ -2452,6 +2452,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
 static void intel_edp_mso_init(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+       struct intel_connector *connector = intel_dp->attached_connector;
+       struct drm_display_info *info = &connector->base.display_info;
        u8 mso;
 
        if (intel_dp->edp_dpcd[0] < DP_EDP_14)
@@ -2470,8 +2472,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
        }
 
        if (mso) {
-               drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
-                           mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
+               drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
+                           mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
+                           info->mso_pixel_overlap);
                if (!HAS_MSO(i915)) {
                        drm_err(&i915->drm, "No source MSO support, disabling\n");
                        mso = 0;
@@ -2479,7 +2482,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
        }
 
        intel_dp->mso_link_count = mso;
-       intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
+       intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
 }
 
 static bool