drm/i915/gen9: Implement Wa4x4STCOptimizationDisable
authorHoath, Nicholas <nicholas.hoath@intel.com>
Thu, 5 Feb 2015 10:47:23 +0000 (10:47 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 13 Feb 2015 22:28:10 +0000 (23:28 +0100)
Move Wa4x4STCOptimizationDisable to gen9_init_workarounds

v2: rebase

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_ringbuffer.c

index 874ec9f..3c64810 100644 (file)
@@ -64,10 +64,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
        }
-
-       /* Wa4x4STCOptimizationDisable:skl */
-       I915_WRITE(CACHE_MODE_1,
-                  _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
index 2ab447c..e35b341 100644 (file)
@@ -902,6 +902,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
                                  GEN9_ENABLE_YV12_BUGFIX);
        }
 
+       /* Wa4x4STCOptimizationDisable:skl */
+       WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
        return 0;
 }