clk: samsung: exynosautov9: add cmu_core clock support

Add CMU_CORE clock which represents Core BUS clocks. The source clocks
of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source
clocks should be provided via device tree. All the gate clocks are
defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus
clocks but not been assigned to any drivers.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com

diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index 96c6c9d..984ecba 100644 (file)
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -956,3 +956,95 @@ static void __init exynosautov9_cmu_top_init(struct device_node *np)
 /* Register CMU_TOP early, as it's a dependency for other early domains */
 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
               exynosautov9_cmu_top_init);
+
+/* ---- CMU_CORE ----------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_CORE (0x1b030000) */
+#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER                              0x0600
+#define CLK_CON_MUX_MUX_CORE_CMUREF                                    0x1000
+#define CLK_CON_DIV_DIV_CLK_CORE_BUSP                                  0x1800
+#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK                 0x2000
+#define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK                        0x2004
+#define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK      0x2008
+
+static const unsigned long core_clk_regs[] __initconst = {
+       PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
+       CLK_CON_MUX_MUX_CORE_CMUREF,
+       CLK_CON_DIV_DIV_CLK_CORE_BUSP,
+       CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
+       CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
+       CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_CORE */
+PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
+
+static const struct samsung_mux_clock core_mux_clks[] __initconst = {
+       MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
+           PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock core_div_clks[] __initconst = {
+       DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
+           CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock core_gate_clks[] __initconst = {
+       GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
+            CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
+            CLK_IS_CRITICAL, 0),
+       GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
+            CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
+            CLK_IS_CRITICAL, 0),
+       GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
+            "dout_core_busp",
+            CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
+            CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info core_cmu_info __initconst = {
+       .mux_clks               = core_mux_clks,
+       .nr_mux_clks            = ARRAY_SIZE(core_mux_clks),
+       .div_clks               = core_div_clks,
+       .nr_div_clks            = ARRAY_SIZE(core_div_clks),
+       .gate_clks              = core_gate_clks,
+       .nr_gate_clks           = ARRAY_SIZE(core_gate_clks),
+       .nr_clk_ids             = CORE_NR_CLK,
+       .clk_regs               = core_clk_regs,
+       .nr_clk_regs            = ARRAY_SIZE(core_clk_regs),
+       .clk_name               = "dout_clkcmu_core_bus",
+};
+
+static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
+{
+       const struct samsung_cmu_info *info;
+       struct device *dev = &pdev->dev;
+
+       info = of_device_get_match_data(dev);
+       exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+       return 0;
+}
+
+static const struct of_device_id exynosautov9_cmu_of_match[] = {
+       {
+               .compatible = "samsung,exynosautov9-cmu-core",
+               .data = &core_cmu_info,
+       }, {
+       },
+};
+
+static struct platform_driver exynosautov9_cmu_driver __refdata = {
+       .driver = {
+               .name = "exynosautov9-cmu",
+               .of_match_table = exynosautov9_cmu_of_match,
+               .suppress_bind_attrs = true,
+       },
+       .probe = exynosautov9_cmu_probe,
+};
+
+static int __init exynosautov9_cmu_init(void)
+{
+       return platform_driver_register(&exynosautov9_cmu_driver);
+}
+core_initcall(exynosautov9_cmu_init);