net/mlx5e: Honor user choice of IPsec replay window size
authorLeon Romanovsky <leonro@nvidia.com>
Sun, 20 Aug 2023 17:58:56 +0000 (20:58 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 20 Dec 2023 16:01:43 +0000 (17:01 +0100)
[ Upstream commit a5e400a985df8041ed4659ed1462aa9134318130 ]

Users can configure IPsec replay window size, but mlx5 driver didn't
honor their choice and set always 32bits. Fix assignment logic to
configure right size from the beginning.

Fixes: 7db21ef4566e ("net/mlx5e: Set IPsec replay sequence numbers")
Reviewed-by: Patrisious Haddad <phaddad@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
include/linux/mlx5/mlx5_ifc.h

index 7d4ceb9..65678e8 100644 (file)
@@ -335,6 +335,27 @@ void mlx5e_ipsec_build_accel_xfrm_attrs(struct mlx5e_ipsec_sa_entry *sa_entry,
                attrs->replay_esn.esn = sa_entry->esn_state.esn;
                attrs->replay_esn.esn_msb = sa_entry->esn_state.esn_msb;
                attrs->replay_esn.overlap = sa_entry->esn_state.overlap;
+               switch (x->replay_esn->replay_window) {
+               case 32:
+                       attrs->replay_esn.replay_window =
+                               MLX5_IPSEC_ASO_REPLAY_WIN_32BIT;
+                       break;
+               case 64:
+                       attrs->replay_esn.replay_window =
+                               MLX5_IPSEC_ASO_REPLAY_WIN_64BIT;
+                       break;
+               case 128:
+                       attrs->replay_esn.replay_window =
+                               MLX5_IPSEC_ASO_REPLAY_WIN_128BIT;
+                       break;
+               case 256:
+                       attrs->replay_esn.replay_window =
+                               MLX5_IPSEC_ASO_REPLAY_WIN_256BIT;
+                       break;
+               default:
+                       WARN_ON(true);
+                       return;
+               }
        }
 
        attrs->dir = x->xso.dir;
index 3245d1c..55b11d8 100644 (file)
@@ -94,7 +94,7 @@ static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn,
 
                if (attrs->dir == XFRM_DEV_OFFLOAD_IN) {
                        MLX5_SET(ipsec_aso, aso_ctx, window_sz,
-                                attrs->replay_esn.replay_window / 64);
+                                attrs->replay_esn.replay_window);
                        MLX5_SET(ipsec_aso, aso_ctx, mode,
                                 MLX5_IPSEC_ASO_REPLAY_PROTECTION);
                }
index fc3db40..f08cd13 100644 (file)
@@ -11936,6 +11936,13 @@ enum {
        MLX5_IPSEC_ASO_INC_SN            = 0x2,
 };
 
+enum {
+       MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
+       MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
+       MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
+       MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
+};
+
 struct mlx5_ifc_ipsec_aso_bits {
        u8         valid[0x1];
        u8         reserved_at_201[0x1];