amvecm: fix G12A eye protect function unused

PD#165151: amvecm: fix G12A eye protect function unused

1. G12A use post matrix as wb adjust module
2. fix 905x eye protect function bug

Change-Id: Ic161cafbb455cf278283d20ef9d93f18c07f5811
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>

diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.c b/drivers/amlogic/media/enhancement/amvecm/amcsc.c
index 71dd48d..b60cd51 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/amcsc.c
+++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.c
@@ -4837,27 +4837,54 @@ static int vpp_eye_protection_process(
                        sdr_process_mode)
                return 0;
 
+       if (vinfo->viu_color_fmt == COLOR_FMT_RGB444)
+               return 0;
        /* post matrix bypass */
-       if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) &&
-               (cur_eye_protect_mode == 0))
-               /* yuv2rgb for eye protect mode */
-               set_vpp_matrix(VPP_MATRIX_POST,
-                       bypass_coeff,
-                       CSC_ON);
-       else /* matrix yuv2rgb for LCD */
-               set_vpp_matrix(VPP_MATRIX_POST,
-                       YUV709l_to_RGB709_coeff,
-                       CSC_ON);
+
+       if (cur_eye_protect_mode == 0) {
+       /* yuv2rgb for eye protect mode */
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A)
+                       mtx_setting(POST2_MTX, MATRIX_YUV709_RGB,
+                               MTX_OFF);
+               else
+                       set_vpp_matrix(VPP_MATRIX_POST,
+                               bypass_coeff,
+                               CSC_ON);
+       } else {/* matrix yuv2rgb for LCD */
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A)
+                       mtx_setting(POST2_MTX, MATRIX_YUV709_RGB,
+                               MTX_ON);
+               else
+                       set_vpp_matrix(VPP_MATRIX_POST,
+                               YUV709l_to_RGB709_coeff,
+                               CSC_ON);
+       }
 
        /* xvycc matrix bypass */
-       if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) &&
-               (cur_eye_protect_mode == 1))
+       if (cur_eye_protect_mode == 1) {
                /*  for eye protect mode */
-               video_rgb_ogo_xvy_mtx_latch &= MTX_RGB2YUVL_RGB_OGO;
-       else /* matrix yuv2rgb for LCD */
-               set_vpp_matrix(VPP_MATRIX_XVYCC,
-                       bypass_coeff,
-                       CSC_ON);
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+                       if (video_rgb_ogo_xvy_mtx)
+                               video_rgb_ogo_xvy_mtx_latch |=
+                                       MTX_RGB2YUVL_RGB_OGO;
+               } else {
+                       if (video_rgb_ogo_xvy_mtx) {
+                               video_rgb_ogo_xvy_mtx_latch |=
+                                       MTX_RGB2YUVL_RGB_OGO;
+                               mtx_en_mux |= XVY_MTX_EN_MASK;
+                       } else
+                               set_vpp_matrix(VPP_MATRIX_XVYCC,
+                                       RGB709_to_YUV709l_coeff,
+                                       CSC_ON);
+               }
+       } else /* matrix yuv2rgb for LCD */
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A)
+                       mtx_setting(POST_MTX, MATRIX_RGB_YUV709,
+                               MTX_OFF);
+               else
+                       set_vpp_matrix(VPP_MATRIX_XVYCC,
+                               bypass_coeff,
+                               CSC_ON);
 
        vpp_set_mtx_en_write();
        return 0;

diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.h b/drivers/amlogic/media/enhancement/amvecm/amcsc.h
index 56d36a0..d22ccb1 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/amcsc.h
+++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.h
@@ -119,6 +119,7 @@ extern signed int saturation_offset;
 extern uint sdr_mode;
 extern uint hdr_flag;
 extern int video_rgb_ogo_xvy_mtx_latch;
+extern int video_rgb_ogo_xvy_mtx;
 
 extern int amvecm_matrix_process(
        struct vframe_s *vf, struct vframe_s *vf_rpt, int flags);

diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.c b/drivers/amlogic/media/enhancement/amvecm/amve.c
index 43c733b..d4b9f3c 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/amve.c
+++ b/drivers/amlogic/media/enhancement/amvecm/amve.c
@@ -138,7 +138,7 @@ module_param(video_rgb_ogo_xvy_mtx, int, 0664);
 MODULE_PARM_DESC(video_rgb_ogo_xvy_mtx,
                "enable/disable video_rgb_ogo_xvy_mtx");
 
-int video_rgb_ogo_xvy_mtx_latch = 1;
+int video_rgb_ogo_xvy_mtx_latch;
 
 static unsigned int assist_cnt;/* ASSIST_SPARE8_REG1; */
 
@@ -540,6 +540,7 @@ void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p)
 {
        int m[24];
        int i;
+       struct vinfo_s *vinfo = get_current_vinfo();
        /* write to registers */
        if (video_rgb_ogo_xvy_mtx) {
                if (video_rgb_ogo_xvy_mtx_latch & MTX_BYPASS_RGB_OGO) {
@@ -552,24 +553,33 @@ void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p)
                        memcpy(m, bypass_coeff, sizeof(int) * 24);
 
                m[3] = p->r_gain * m[3] / COEFF_NORM(1.0);
-               m[4] = p->r_gain * m[4] / COEFF_NORM(1.0);
-               m[5] = p->r_gain * m[5] / COEFF_NORM(1.0);
-               m[6] = p->g_gain * m[6] / COEFF_NORM(1.0);
+               m[4] = p->g_gain * m[4] / COEFF_NORM(1.0);
+               m[5] = p->b_gain * m[5] / COEFF_NORM(1.0);
+               m[6] = p->r_gain * m[6] / COEFF_NORM(1.0);
                m[7] = p->g_gain * m[7] / COEFF_NORM(1.0);
-               m[8] = p->g_gain * m[8] / COEFF_NORM(1.0);
-               m[9] = p->b_gain * m[9] / COEFF_NORM(1.0);
-               m[10] = p->b_gain * m[10] / COEFF_NORM(1.0);
+               m[8] = p->b_gain * m[8] / COEFF_NORM(1.0);
+               m[9] = p->r_gain * m[9] / COEFF_NORM(1.0);
+               m[10] = p->g_gain * m[10] / COEFF_NORM(1.0);
                m[11] = p->b_gain * m[11] / COEFF_NORM(1.0);
 
-               m[18] = (p->r_pre_offset + m[18] + 1024)
-                       * p->r_gain / COEFF_NORM(1.0)
-                       - p->r_gain + p->r_post_offset;
-               m[19] = (p->g_pre_offset + m[19] + 1024)
-                       * p->g_gain / COEFF_NORM(1.0)
-                       - p->g_gain + p->g_post_offset;
-               m[20] = (p->b_pre_offset + m[20] + 1024)
-                       * p->b_gain / COEFF_NORM(1.0)
-                       - p->b_gain + p->b_post_offset;
+               if (vinfo->viu_color_fmt == COLOR_FMT_RGB444) {
+                       m[18] = (p->r_pre_offset + m[18] + 1024)
+                               * p->r_gain / COEFF_NORM(1.0)
+                               - p->r_gain + p->r_post_offset;
+                       m[19] = (p->g_pre_offset + m[19] + 1024)
+                               * p->g_gain / COEFF_NORM(1.0)
+                               - p->g_gain + p->g_post_offset;
+                       m[20] = (p->b_pre_offset + m[20] + 1024)
+                               * p->b_gain / COEFF_NORM(1.0)
+                               - p->b_gain + p->b_post_offset;
+               } else {
+                       m[0] = p->r_gain * p->r_pre_offset / COEFF_NORM(1.0) +
+                               p->r_post_offset;
+                       m[1] = p->g_gain * p->g_pre_offset / COEFF_NORM(1.0) +
+                               p->g_post_offset;
+                       m[2] = p->b_gain * p->b_pre_offset / COEFF_NORM(1.0) +
+                               p->b_post_offset;
+               }
 
                for (i = 18; i < 21; i++) {
                        if (m[i] > 1023)
@@ -578,6 +588,51 @@ void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p)
                                m[i] = -1024;
                }
 
+               if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
+                       WRITE_VPP_REG_BITS(VPP_POST_MATRIX_EN_CTRL,
+                               p->en, 0, 1);
+                       WRITE_VPP_REG(VPP_POST_MATRIX_PRE_OFFSET0_1,
+                               ((m[0] & 0xfff) << 16)
+                               | (m[1] & 0xfff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_PRE_OFFSET2,
+                               m[2] & 0xfff);
+                       WRITE_VPP_REG(VPP_POST_MATRIX_COEF00_01,
+                               ((m[3] & 0x1fff) << 16)
+                               | (m[4] & 0x1fff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_COEF02_10,
+                               ((m[5]  & 0x1fff) << 16)
+                               | (m[6] & 0x1fff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_COEF11_12,
+                               ((m[7] & 0x1fff) << 16)
+                               | (m[8] & 0x1fff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_COEF20_21,
+                               ((m[9] & 0x1fff) << 16)
+                               | (m[10] & 0x1fff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_COEF22,
+                               m[11] & 0x1fff);
+                       if (m[21]) {
+                               WRITE_VPP_REG(VPP_POST_MATRIX_COEF13_14,
+                                       ((m[12] & 0x1fff) << 16)
+                                       | (m[13] & 0x1fff));
+                               WRITE_VPP_REG(VPP_POST_MATRIX_COEF15_25,
+                                       ((m[14] & 0x1fff) << 16)
+                                       | (m[17] & 0x1fff));
+                               WRITE_VPP_REG(VPP_POST_MATRIX_COEF23_24,
+                                       ((m[15] & 0x1fff) << 16)
+                                       | (m[16] & 0x1fff));
+                       }
+                       WRITE_VPP_REG(VPP_POST_MATRIX_OFFSET0_1,
+                               ((m[18] & 0xfff) << 16)
+                               | (m[19] & 0xfff));
+                       WRITE_VPP_REG(VPP_POST_MATRIX_OFFSET2,
+                               m[20] & 0xfff);
+                       WRITE_VPP_REG_BITS(VPP_POST_MATRIX_CLIP,
+                               m[21], 3, 2);
+                       WRITE_VPP_REG_BITS(VPP_POST_MATRIX_CLIP,
+                               m[22], 5, 3);
+                       return;
+               }
+
                WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, p->en, 6, 1);
                WRITE_VPP_REG_BITS(VPP_MATRIX_CTRL, 3, 8, 2);