ppc_4xx: Fix post spr.c for PPC405

post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>

diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index 3e74634..c12e378 100644 (file)
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -80,7 +80,9 @@ static struct {
        {0x107, "SPRG7",        0x00000000,     0x00000000},
        {0x10c, "TBL",          0x00000000,     0x00000000},
        {0x10d, "TBU",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x11e, "PIR",          0x0000000f,     0x00000000},
+#endif
        {0x130, "DBSR",         0x00000000,     0x00000000},
        {0x134, "DBCR0",        0x00000000,     0x00000000},
        {0x135, "DBCR1",        0x00000000,     0x00000000},
@@ -95,6 +97,7 @@ static struct {
        {0x13f, "DVC2",         0x00000000,     0x00000000},
        {0x150, "TSR",          0x00000000,     0x00000000},
        {0x154, "TCR",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x190, "IVOR0",        0x0000fff0,     0x00000100},
        {0x191, "IVOR1",        0x0000fff0,     0x00000200},
        {0x192, "IVOR2",        0x0000fff0,     0x00000300},
@@ -111,6 +114,7 @@ static struct {
        {0x19d, "IVOR13",       0x0000fff0,     0x00001300},
        {0x19e, "IVOR14",       0x0000fff0,     0x00001400},
        {0x19f, "IVOR15",       0x0000fff0,     0x00002000},
+#endif
        {0x23a, "MCSRR0",       0x00000000,     0x00000000},
        {0x23b, "MCSRR1",       0x00000000,     0x00000000},
        {0x23c, "MCSR",         0x00000000,     0x00000000},
@@ -131,8 +135,10 @@ static struct {
        {0x395, "DTV1",         0x00000000,     0x00000000},
        {0x396, "DTV2",         0x00000000,     0x00000000},
        {0x397, "DTV3",         0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x398, "DVLIM",        0x0fc1f83f,     0x0001f800},
        {0x399, "IVLIM",        0x0fc1f83f,     0x0001f800},
+#endif
        {0x39b, "RSTCFG",       0x00000000,     0x00000000},
        {0x39c, "DCDBTRL",      0x00000000,     0x00000000},
        {0x39d, "DCDBTRH",      0x00000000,     0x00000000},