return ret;
if (limits.vco2.maxfreq) {
+ NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
+ pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P);
+
reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
nv_wr32(dev, pll_reg, 0x10000611);
nv_wr32(dev, pll_reg + 8,
reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
} else {
+ NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n",
+ pclk, ret, pll.N1, pll.M1, pll.log2P);
+
reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
nv_wr32(dev, pll_reg, 0x50000610);
nv_wr32(dev, pll_reg + 4, reg1 |