+2011-04-20 Catherine Moore <clm@codesourcery.com>
+ David Ung <davidu@mips.com>
+
+ * gas/mips/24k-branch-delay-1.d: New.
+ * gas/mips/24k-branch-delay-1.s: New.
+ * gas/mips/24k-triple-stores-1.d: New.
+ * gas/mips/24k-triple-stores-1.s: New.
+ * gas/mips/24k-triple-stores-2.d: New.
+ * gas/mips/24k-triple-stores-2.s: New.
+ * gas/mips/24k-triple-stores-3.d: New.
+ * gas/mips/24k-triple-stores-3.s: New.
+ * gas/mips/24k-triple-stores-4.s: New.
+ * gas/mips/24k-triple-stores-4.d: New.
+ * gas/mips/24k-triple-stores-5.d: New.
+ * gas/mips/24k-triple-stores-5.s: New.
+ * gas/mips/24k-triple-stores-6.d: New.
+ * gas/mips/24k-triple-stores-6.s: New.
+ * gas/mips/24k-triple-stores-7.d: New.
+ * gas/mips/24k-triple-stores-7.s: New.
+ * gas/mips/24k-triple-stores-8.d: New.
+ * gas/mips/24k-triple-stores-8.s: New.
+ * gas/mips/24k-triple-stores-9.d: New.
+ * gas/mips/24k-triple-stores-9.s: New.
+ * gas/mips/24k-triple-stores-10.d: New.
+ * gas/mips/24k-triple-stores-10.s: New.
+ * gas/mips/24k-triple-stores-11.d: New.
+ * gas/mips/24k-triple-stores-11.s: New.
+ * gas/mips/mips.exp: Invoke new tests.
+
2011-04-19 Nick Clifton <nickc@redhat.com>
* gas/arm/mrs-msr-thumb-v7e-m.s: Restore name of basepri_max
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Delay slot filling
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <func>:
+ 0: 24620005 addiu v0,v1,5
+ 4: 8c440000 lw a0,0\(v0\)
+ 8: ac430000 sw v1,0\(v0\)
+ c: ac430008 sw v1,8\(v0\)
+ 10: 00000000 nop
+ 14: 10600002 beqz v1,20 <func\+0x20>
+ 18: ac430010 sw v1,16\(v0\)
+ 1c: 8c430008 lw v1,8\(v0\)
+ 20: 8c450010 lw a1,16\(v0\)
+ ...
--- /dev/null
+# Test that we don't move store into delay slots
+
+ .text
+func:
+ addiu $2,$3,5
+ lw $4,0($2)
+ sw $3,0($2)
+ sw $3,8($2)
+ sw $3,16($2)
+ beq $3,0,.L1
+ lw $3,8($2)
+.L1:
+ lw $5,16($2)
+ .p2align 4
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Opcode Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a3a20000 sb v0,0\(sp\)
+ 4: 00000000 nop
+ 8: a3a30008 sb v1,8\(sp\)
+ c: a3a40010 sb a0,16\(sp\)
+ 10: 00000000 nop
+ 14: a3a50018 sb a1,24\(sp\)
+ 18: a3a60020 sb a2,32\(sp\)
+ 1c: a7a20000 sh v0,0\(sp\)
+ 20: a7a30008 sh v1,8\(sp\)
+ 24: 00000000 nop
+ 28: a7a40010 sh a0,16\(sp\)
+ 2c: a7a50018 sh a1,24\(sp\)
+ 30: 00000000 nop
+ 34: a7a60020 sh a2,32\(sp\)
+ 38: afa20000 sw v0,0\(sp\)
+ 3c: afa30008 sw v1,8\(sp\)
+ 40: 00000000 nop
+ 44: afa40010 sw a0,16\(sp\)
+ 48: afa50018 sw a1,24\(sp\)
+ 4c: 00000000 nop
+ 50: afa60020 sw a2,32\(sp\)
+ 54: bba20000 swr v0,0\(sp\)
+ 58: bba30008 swr v1,8\(sp\)
+ 5c: 00000000 nop
+ 60: bba40010 swr a0,16\(sp\)
+ 64: bba50018 swr a1,24\(sp\)
+ 68: 00000000 nop
+ 6c: bba60020 swr a2,32\(sp\)
+ 70: aba20000 swl v0,0\(sp\)
+ 74: aba30008 swl v1,8\(sp\)
+ 78: 00000000 nop
+ 7c: aba40010 swl a0,16\(sp\)
+ 80: aba50018 swl a1,24\(sp\)
+ 84: 00000000 nop
+ 88: aba60020 swl a2,32\(sp\)
+ 8c: e3a20000 sc v0,0\(sp\)
+ 90: e3a30008 sc v1,8\(sp\)
+ 94: 00000000 nop
+ 98: e3a40010 sc a0,16\(sp\)
+ 9c: e3a50018 sc a1,24\(sp\)
+ a0: 00000000 nop
+ a4: e3a60020 sc a2,32\(sp\)
+ a8: e7a20000 swc1 \$f2,0\(sp\)
+ ac: e7a30008 swc1 \$f3,8\(sp\)
+ b0: 00000000 nop
+ b4: e7a40010 swc1 \$f4,16\(sp\)
+ b8: e7a50018 swc1 \$f5,24\(sp\)
+ bc: 00000000 nop
+ c0: e7a60020 swc1 \$f6,32\(sp\)
+ c4: eba20000 swc2 \$2,0\(sp\)
+ c8: eba30008 swc2 \$3,8\(sp\)
+ cc: 00000000 nop
+ d0: eba40010 swc2 \$4,16\(sp\)
+ d4: eba50018 swc2 \$5,24\(sp\)
+ d8: 00000000 nop
+ dc: eba60020 swc2 \$6,32\(sp\)
+ e0: f7a20000 sdc1 \$f2,0\(sp\)
+ e4: f7a30008 sdc1 \$f3,8\(sp\)
+ e8: 00000000 nop
+ ec: f7a40010 sdc1 \$f4,16\(sp\)
+ f0: f7a50018 sdc1 \$f5,24\(sp\)
+ f4: 00000000 nop
+ f8: f7a60020 sdc1 \$f6,32\(sp\)
+ fc: fba20000 sdc2 \$2,0\(sp\)
+ 100: fba30008 sdc2 \$3,8\(sp\)
+ 104: 00000000 nop
+ 108: fba40010 sdc2 \$4,16\(sp\)
+ 10c: fba50018 sdc2 \$5,24\(sp\)
+ 110: 00000000 nop
+ 114: fba60020 sdc2 \$6,32\(sp\)
+ 118: 4d090008 swxc1 \$f0,t1\(t0\)
+ 11c: 00000000 nop
+ 120: 4d0a0808 swxc1 \$f1,t2\(t0\)
+ 124: 4d0b1008 swxc1 \$f2,t3\(t0\)
+ 128: 00000000 nop
+ 12c: 4d0c1808 swxc1 \$f3,t4\(t0\)
+ 130: 4d0d2008 swxc1 \$f4,t5\(t0\)
+ 134: 00000000 nop
+ 138: 4d090009 sdxc1 \$f0,t1\(t0\)
+ 13c: 4d0a1009 sdxc1 \$f2,t2\(t0\)
+ 140: 00000000 nop
+ 144: 4d0b2009 sdxc1 \$f4,t3\(t0\)
+ 148: 4d0c3009 sdxc1 \$f6,t4\(t0\)
+ 14c: 00000000 nop
+ 150: 4d0d4009 sdxc1 \$f8,t5\(t0\)
+ 154: 4d09000d suxc1 \$f0,t1\(t0\)
+ 158: 00000000 nop
+ 15c: 4d0a100d suxc1 \$f2,t2\(t0\)
+ 160: 4d0b200d suxc1 \$f4,t3\(t0\)
+ 164: 00000000 nop
+ 168: 4d0c300d suxc1 \$f6,t4\(t0\)
+ 16c: 4d0d400d suxc1 \$f8,t5\(t0\)
+ ...
--- /dev/null
+# integer stores
+
+ sb $2,0($sp)
+ sb $3,8($sp)
+ sb $4,16($sp)
+ sb $5,24($sp)
+ sb $6,32($sp)
+
+ sh $2,0($sp)
+ sh $3,8($sp)
+ sh $4,16($sp)
+ sh $5,24($sp)
+ sh $6,32($sp)
+
+ sw $2,0($sp)
+ sw $3,8($sp)
+ sw $4,16($sp)
+ sw $5,24($sp)
+ sw $6,32($sp)
+
+ swr $2,0($sp)
+ swr $3,8($sp)
+ swr $4,16($sp)
+ swr $5,24($sp)
+ swr $6,32($sp)
+
+ swl $2,0($sp)
+ swl $3,8($sp)
+ swl $4,16($sp)
+ swl $5,24($sp)
+ swl $6,32($sp)
+
+ sc $2,0($sp)
+ sc $3,8($sp)
+ sc $4,16($sp)
+ sc $5,24($sp)
+ sc $6,32($sp)
+
+# floating point stores
+
+ swc1 $2,0($sp)
+ swc1 $3,8($sp)
+ swc1 $4,16($sp)
+ swc1 $5,24($sp)
+ swc1 $6,32($sp)
+
+ swc2 $2,0($sp)
+ swc2 $3,8($sp)
+ swc2 $4,16($sp)
+ swc2 $5,24($sp)
+ swc2 $6,32($sp)
+
+ sdc1 $2,0($sp)
+ sdc1 $3,8($sp)
+ sdc1 $4,16($sp)
+ sdc1 $5,24($sp)
+ sdc1 $6,32($sp)
+
+ sdc2 $2,0($sp)
+ sdc2 $3,8($sp)
+ sdc2 $4,16($sp)
+ sdc2 $5,24($sp)
+ sdc2 $6,32($sp)
+
+ swxc1 $f0,$9($8)
+ swxc1 $f1,$10($8)
+ swxc1 $f2,$11($8)
+ swxc1 $f3,$12($8)
+ swxc1 $f4,$13($8)
+
+ sdxc1 $f0,$9($8)
+ sdxc1 $f2,$10($8)
+ sdxc1 $f4,$11($8)
+ sdxc1 $f6,$12($8)
+ sdxc1 $f8,$13($8)
+
+ suxc1 $f0,$9($8)
+ suxc1 $f2,$10($8)
+ suxc1 $f4,$11($8)
+ suxc1 $f6,$12($8)
+ suxc1 $f8,$13($8)
+
+# Force at least 8 (non-delay-slot) zero bytes,to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Intervening data #2)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a1020000 sb v0,0\(t0\)
+ 4: 00000000 nop
+ 8: a1030008 sb v1,8\(t0\)
+ c: a1040010 sb a0,16\(t0\)
--- /dev/null
+ .text
+ sb $2,0($8)
+ sb $3,8($8)
+ .data
+ .word 1
+ .text
+ sb $4,16($8)
+ .data
--- /dev/null
+#objdump: -d
+#as: -mfix-24k
+#name: 24K: Triple Store (gprel relocs)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: 00842020 add a0,a0,a0
+ 4: 00842020 add a0,a0,a0
+ 8: 00842020 add a0,a0,a0
+ c: 00842020 add a0,a0,a0
+ 10: af820000 sw v0,0\(gp\)
+ 14: af830000 sw v1,0\(gp\)
+ 18: 00000000 nop
+ 1c: af840000 sw a0,0\(gp\)
+
--- /dev/null
+ .text
+ add $4,$4,$4
+ add $4,$4,$4
+ add $4,$4,$4
+ add $4,$4,$4
+ sw $2,%gp_rel(sym1)($28)
+ sw $3,%gp_rel(sym2)($28)
+ sw $4,%gp_rel(sym3)($28)
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Range Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a3a20000 sb v0,0\(sp\)
+ 4: 00000000 nop
+ 8: a3a3000a sb v1,10\(sp\)
+ c: a3a4001f sb a0,31\(sp\)
+ 10: 0000000d break
+ 14: a7a20000 sh v0,0\(sp\)
+ 18: a7a3fff0 sh v1,-16\(sp\)
+ 1c: a7a4ffe0 sh a0,-32\(sp\)
+ 20: 0000000d break
+ 24: afa20000 sw v0,0\(sp\)
+ 28: afa3fff8 sw v1,-8\(sp\)
+ 2c: 00000000 nop
+ 30: afa40008 sw a0,8\(sp\)
+ 34: 0000000d break
+ 38: bba20000 swr v0,0\(sp\)
+ 3c: bba3fff0 swr v1,-16\(sp\)
+ 40: bba40010 swr a0,16\(sp\)
+ 44: 0000000d break
+ 48: aba20000 swl v0,0\(sp\)
+ 4c: aba30008 swl v1,8\(sp\)
+ 50: 00000000 nop
+ 54: aba40010 swl a0,16\(sp\)
+ 58: aba50018 swl a1,24\(sp\)
+ 5c: 00000000 nop
+ 60: aba60000 swl a2,0\(sp\)
+ 64: 0000000d break
+ 68: e3a20020 sc v0,32\(sp\)
+ 6c: e3a30008 sc v1,8\(sp\)
+ 70: e3a4fff8 sc a0,-8\(sp\)
+ 74: 00000000 nop
+ 78: e3a50000 sc a1,0\(sp\)
+ 7c: e3a60020 sc a2,32\(sp\)
+ \.\.\.
--- /dev/null
+# Check for range
+
+ sb $2,0($sp)
+ sb $3,10($sp)
+ sb $4,31($sp)
+ break
+
+ sh $2,0($sp)
+ sh $3,-16($sp)
+ sh $4,-32($sp)
+ break
+
+ sw $2,0($sp)
+ sw $3,-8($sp)
+ sw $4,8($sp)
+ break
+
+ swr $2,0($sp)
+ swr $3,-16($sp)
+ swr $4,16($sp)
+ break
+
+ swl $2,0($sp)
+ swl $3,8($sp)
+ swl $4,16($sp)
+ swl $5,24($sp)
+ swl $6,0($sp)
+ break
+
+ sc $2,32($sp)
+ sc $3,8($sp)
+ sc $4,-8($sp)
+ sc $5,0($sp)
+ sc $6,32($sp)
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Double-word Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: a3a2000b sb v0,11\(sp\)
+ 4: 00000000 nop
+ 8: a3a3000b sb v1,11\(sp\)
+ c: a3a40004 sb a0,4\(sp\)
+ 10: 0000000d break
+ 14: a3a20000 sb v0,0\(sp\)
+ 18: a3a3000b sb v1,11\(sp\)
+ 1c: a3a40005 sb a0,5\(sp\)
+ 20: 0000000d break
+ 24: a3a20007 sb v0,7\(sp\)
+ 28: a3a3000b sb v1,11\(sp\)
+ 2c: 00000000 nop
+ 30: a3a40010 sb a0,16\(sp\)
+ 34: 0000000d break
+ 38: a1020000 sb v0,0\(t0\)
+ 3c: a1030008 sb v1,8\(t0\)
+ 40: 00000000 nop
+ 44: a1040009 sb a0,9\(t0\)
+ 48: 0000000d break
+ 4c: a7a20000 sh v0,0\(sp\)
+ 50: a7a3ffe1 sh v1,-31\(sp\)
+ 54: a7a4ffe2 sh a0,-30\(sp\)
+ 58: 0000000d break
+ 5c: a7a20006 sh v0,6\(sp\)
+ 60: a7a30008 sh v1,8\(sp\)
+ 64: 00000000 nop
+ 68: a7a40010 sh a0,16\(sp\)
+ 6c: 0000000d break
+ 70: a5020001 sh v0,1\(t0\)
+ 74: a5030003 sh v1,3\(t0\)
+ 78: 00000000 nop
+ 7c: a504000b sh a0,11\(t0\)
+ 80: 0000000d break
+ 84: afa20008 sw v0,8\(sp\)
+ 88: afa3fff8 sw v1,-8\(sp\)
+ 8c: afa40008 sw a0,8\(sp\)
+ 90: 0000000d break
+ 94: afa20004 sw v0,4\(sp\)
+ 98: afa30008 sw v1,8\(sp\)
+ 9c: 00000000 nop
+ a0: afa40010 sw a0,16\(sp\)
+ a4: 0000000d break
+ a8: ad020003 sw v0,3\(t0\)
+ ac: ad030007 sw v1,7\(t0\)
+ b0: 00000000 nop
+ b4: ad04000f sw a0,15\(t0\)
+ b8: 0000000d break
+ bc: aba20004 swl v0,4\(sp\)
+ c0: aba3000a swl v1,10\(sp\)
+ c4: 00000000 nop
+ c8: aba40011 swl a0,17\(sp\)
+ cc: 0000000d break
+ d0: aba20007 swl v0,7\(sp\)
+ d4: aba3000c swl v1,12\(sp\)
+ d8: 00000000 nop
+ dc: aba40010 swl a0,16\(sp\)
+ e0: 0000000d break
+ e4: aba20000 swl v0,0\(sp\)
+ e8: aba3000c swl v1,12\(sp\)
+ ec: 00000000 nop
+ f0: aba40017 swl a0,23\(sp\)
+ f4: 0000000d break
+ f8: a9020003 swl v0,3\(t0\)
+ fc: a9030008 swl v1,8\(t0\)
+ 100: 00000000 nop
+ 104: a904000c swl a0,12\(t0\)
+ 108: 0000000d break
+ 10c: aba20000 swl v0,0\(sp\)
+ 110: aba3000c swl v1,12\(sp\)
+ 114: 00000000 nop
+ 118: bba40017 swr a0,23\(sp\)
+ 11c: 0000000d break
+ 120: a9020005 swl v0,5\(t0\)
+ 124: a9030011 swl v1,17\(t0\)
+ 128: 00000000 nop
+ 12c: b904001c swr a0,28\(t0\)
+ 130: 0000000d break
+ \.\.\.
--- /dev/null
+# Assume to be on the same line (within 32bytes)
+# Check for individual different double words
+
+ # safe
+ sb $2,11($sp)
+ sb $3,11($sp)
+ sb $4,4($sp)
+ break
+
+ # safe
+ sb $2,0($sp)
+ sb $3,11($sp)
+ sb $4,5($sp)
+ break
+
+ # edge case
+ sb $2,7($sp)
+ sb $3,11($sp)
+ sb $4,16($sp)
+ break
+
+ # edge case (unaligned)
+ sb $2,0($8)
+ sb $3,8($8)
+ sb $4,9($8)
+ break
+
+ sh $2,0($sp)
+ sh $3,-31($sp)
+ sh $4,-30($sp)
+ break
+
+ # edge case
+ sh $2,6($sp)
+ sh $3,8($sp)
+ sh $4,16($sp)
+ break
+
+ # edge case (unaligned)
+ sh $2,1($8)
+ sh $3,3($8)
+ sh $4,11($8)
+ break
+
+ sw $2,8($sp)
+ sw $3,-8($sp)
+ sw $4,8($sp)
+ break
+
+ # edge case
+ sw $2,4($sp)
+ sw $3,8($sp)
+ sw $4,16($sp)
+ break
+
+ # edge case (unaligned)
+ sw $2,3($8)
+ sw $3,7($8)
+ sw $4,15($8)
+ break
+
+ swl $2,4($sp)
+ swl $3,10($sp)
+ swl $4,17($sp)
+ break
+
+ # edge case
+ swl $2,7($sp)
+ swl $3,12($sp)
+ swl $4,16($sp)
+ break
+
+ # edge case
+ swl $2,0($sp)
+ swl $3,12($sp)
+ swl $4,23($sp)
+ break
+
+ # edge case (unaligned)
+ swl $2,3($8)
+ swl $3,8($8)
+ swl $4,12($8)
+ break
+
+ # mix swl & swr
+ swl $2,0($sp)
+ swl $3,12($sp)
+ swr $4,23($sp)
+ break
+
+ # mix swl & swr
+ swl $2,5($8)
+ swl $3,17($8)
+ swr $4,28($8)
+ break
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Range Check >= 32)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a113000a sb s3,10\(t0\)
+ 4: 00000000 nop
+ 8: a5130001 sh s3,1\(t0\)
+ c: a1130020 sb s3,32\(t0\)
+ 10: 0000000d break
+ 14: a113000a sb s3,10\(t0\)
+ 18: a1130001 sb s3,1\(t0\)
+ 1c: a5130020 sh s3,32\(t0\)
+ 20: 0000000d break
+ 24: a1130021 sb s3,33\(t0\)
+ 28: a5130037 sh s3,55\(t0\)
+ 2c: 00000000 nop
+ 30: a1130040 sb s3,64\(t0\)
+ 34: 0000000d break
+ 38: a1130021 sb s3,33\(t0\)
+ 3c: a1130037 sb s3,55\(t0\)
+ 40: a5130040 sh s3,64\(t0\)
+ 44: 0000000d break
+ 48: a113000c sb s3,12\(t0\)
+ 4c: ad130001 sw s3,1\(t0\)
+ 50: 00000000 nop
+ 54: a1130020 sb s3,32\(t0\)
+ 58: 0000000d break
+ 5c: a113000c sb s3,12\(t0\)
+ 60: a1130001 sb s3,1\(t0\)
+ 64: ad130020 sw s3,32\(t0\)
+ 68: 0000000d break
+ 6c: a1130023 sb s3,35\(t0\)
+ 70: ad130037 sw s3,55\(t0\)
+ 74: 00000000 nop
+ 78: a1130040 sb s3,64\(t0\)
+ 7c: 0000000d break
+ 80: a1130023 sb s3,35\(t0\)
+ 84: a1130037 sb s3,55\(t0\)
+ 88: ad130040 sw s3,64\(t0\)
+ 8c: 0000000d break
+ 90: a1130010 sb s3,16\(t0\)
+ 94: f5000001 sdc1 \$f0,1\(t0\)
+ 98: 00000000 nop
+ 9c: a1130020 sb s3,32\(t0\)
+ a0: 0000000d break
+ a4: a1130010 sb s3,16\(t0\)
+ a8: a1130001 sb s3,1\(t0\)
+ ac: f5000020 sdc1 \$f0,32\(t0\)
+ b0: 0000000d break
+ b4: a1130027 sb s3,39\(t0\)
+ b8: f5000037 sdc1 \$f0,55\(t0\)
+ bc: 00000000 nop
+ c0: a1130040 sb s3,64\(t0\)
+ c4: 0000000d break
+ c8: a1130027 sb s3,39\(t0\)
+ cc: a1130037 sb s3,55\(t0\)
+ d0: f5000040 sdc1 \$f0,64\(t0\)
+ d4: 0000000d break
+ ...
--- /dev/null
+ # Range check for safe case after alignment its range >= 32.
+
+ sb $s3,10($t0)
+ sh $s3,1($t0)
+ sb $s3,32($t0)
+ break
+ sb $s3,10($t0)
+ sb $s3,1($t0)
+ sh $s3,32($t0)
+ break
+ sb $s3,33($t0)
+ sh $s3,55($t0)
+ sb $s3,64($t0)
+ break
+ sb $s3,33($t0)
+ sb $s3,55($t0)
+ sh $s3,64($t0)
+ break
+
+ sb $s3,12($t0)
+ sw $s3,1($t0)
+ sb $s3,32($t0)
+ break
+ sb $s3,12($t0)
+ sb $s3,1($t0)
+ sw $s3,32($t0)
+ break
+ sb $s3,35($t0)
+ sw $s3,55($t0)
+ sb $s3,64($t0)
+ break
+ sb $s3,35($t0)
+ sb $s3,55($t0)
+ sw $s3,64($t0)
+ break
+
+ sb $s3,16($t0)
+ sdc1 $f0,1($t0)
+ sb $s3,32($t0)
+ break
+ sb $s3,16($t0)
+ sb $s3,1($t0)
+ sdc1 $f0,32($t0)
+ break
+ sb $s3,39($t0)
+ sdc1 $f0,55($t0)
+ sb $s3,64($t0)
+ break
+ sb $s3,39($t0)
+ sb $s3,55($t0)
+ sdc1 $f0,64($t0)
+ break
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Mix byte/half/word size check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a5020007 sh v0,7\(t0\)
+ 4: 00000000 nop
+ 8: a1030000 sb v1,0\(t0\)
+ c: ad040001 sw a0,1\(t0\)
+ 10: 0000000d break
+ 14: a5020016 sh v0,22\(t0\)
+ 18: a103000f sb v1,15\(t0\)
+ 1c: 00000000 nop
+ 20: ad040018 sw a0,24\(t0\)
+ 24: 0000000d break
+ 28: a5020000 sh v0,0\(t0\)
+ 2c: a1030009 sb v1,9\(t0\)
+ 30: ad040002 sw a0,2\(t0\)
+ 34: 0000000d break
+ 38: a5020006 sh v0,6\(t0\)
+ 3c: a1030010 sb v1,16\(t0\)
+ 40: 00000000 nop
+ 44: ad04000c sw a0,12\(t0\)
+ 48: 0000000d break
+ 4c: a502000a sh v0,10\(t0\)
+ 50: a103000f sb v1,15\(t0\)
+ 54: ad040004 sw a0,4\(t0\)
+ 58: 0000000d break
+ 5c: a502000a sh v0,10\(t0\)
+ 60: a1030010 sb v1,16\(t0\)
+ 64: 00000000 nop
+ 68: ad040004 sw a0,4\(t0\)
+ 6c: 0000000d break
+ \.\.\.
--- /dev/null
+# Mix byte/half/word sizes with arbitary base register.
+
+ # safe
+ sh $2,7($8)
+ sb $3,0($8)
+ sw $4,1($8)
+ break
+
+ # nop
+ sh $2,22($8)
+ sb $3,15($8)
+ sw $4,24($8)
+ break
+
+ # safe
+ sh $2,0($8)
+ sb $3,9($8)
+ sw $4,2($8)
+ break
+
+ # nop
+ sh $2,6($8)
+ sb $3,16($8)
+ sw $4,12($8)
+ break
+
+ # safe
+ sh $2,10($8)
+ sb $3,15($8)
+ sw $4,4($8)
+ break
+
+ # nop
+ sh $2,10($8)
+ sb $3,16($8)
+ sw $4,4($8)
+ break
+
+# Force at least 8 (non-delay-slot) zero bytes,to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Store Macro Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: abbf0050 swl ra,80\(sp\)
+ 4: 00000000 nop
+ 8: bbbf0053 swr ra,83\(sp\)
+ c: abb30058 swl s3,88\(sp\)
+ 10: bbb3005b swr s3,91\(sp\)
+ 14: abbe0060 swl s8,96\(sp\)
+ 18: bbbe0063 swr s8,99\(sp\)
+ 1c: 0000000d break
+ 20: a3bf0051 sb ra,81\(sp\)
+ 24: 001f0a02 srl at,ra,0x8
+ 28: a3a10050 sb at,80\(sp\)
+ 2c: a3b30059 sb s3,89\(sp\)
+ 30: 00130a02 srl at,s3,0x8
+ 34: a3a10058 sb at,88\(sp\)
+ 38: a3be0061 sb s8,97\(sp\)
+ 3c: 001e0a02 srl at,s8,0x8
+ 40: a3a10060 sb at,96\(sp\)
+ 44: 0000000d break
+ 48: e7a00050 swc1 \$f0,80\(sp\)
+ 4c: e7a20058 swc1 \$f2,88\(sp\)
+ 50: 00000000 nop
+ 54: e7a40060 swc1 \$f4,96\(sp\)
+ 58: 0000000d break
+ 5c: f7a00050 sdc1 \$f0,80\(sp\)
+ 60: f7a20058 sdc1 \$f2,88\(sp\)
+ 64: 00000000 nop
+ 68: f7a40060 sdc1 \$f4,96\(sp\)
+ 6c: 0000000d break
+ \.\.\.
--- /dev/null
+ # Store macros
+
+ usw $ra,80($sp)
+ usw $s3,88($sp)
+ usw $s8,96($sp)
+ break
+
+ ush $ra,80($sp)
+ ush $s3,88($sp)
+ ush $s8,96($sp)
+ break
+
+ # swc1 macro
+ s.s $f0,80($sp)
+ s.s $f2,88($sp)
+ s.s $f4,96($sp)
+ break
+
+ # sdc1 macro
+ s.d $f0,80($sp)
+ s.d $f2,88($sp)
+ s.d $f4,96($sp)
+break
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Extended Range Check)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a1130004 sb s3,4\(t0\)
+ 4: 00000000 nop
+ 8: ad130008 sw s3,8\(t0\)
+ c: a113000f sb s3,15\(t0\)
+ 10: 0000000d break
+ 14: a1130003 sb s3,3\(t0\)
+ 18: ad130008 sw s3,8\(t0\)
+ 1c: 00000000 nop
+ 20: a113000f sb s3,15\(t0\)
+ 24: 0000000d break
+ 28: ad13001c sw s3,28\(t0\)
+ 2c: ad130008 sw s3,8\(t0\)
+ 30: a113001f sb s3,31\(t0\)
+ 34: 0000000d break
+ 38: a1130005 sb s3,5\(t0\)
+ 3c: ad130009 sw s3,9\(t0\)
+ 40: a1130010 sb s3,16\(t0\)
+ 44: 0000000d break
+ 48: a1130004 sb s3,4\(t0\)
+ 4c: ad130009 sw s3,9\(t0\)
+ 50: 00000000 nop
+ 54: a1130010 sb s3,16\(t0\)
+ 58: 0000000d break
+ 5c: a1130006 sb s3,6\(t0\)
+ 60: a5130008 sh s3,8\(t0\)
+ 64: a113000f sb s3,15\(t0\)
+ 68: 0000000d break
+ 6c: a1130005 sb s3,5\(t0\)
+ 70: a5130008 sh s3,8\(t0\)
+ 74: 00000000 nop
+ 78: a113000f sb s3,15\(t0\)
+ 7c: 0000000d break
+ 80: a513001e sh s3,30\(t0\)
+ 84: a5130008 sh s3,8\(t0\)
+ 88: a113001f sb s3,31\(t0\)
+ 8c: 0000000d break
+ 90: a1130007 sb s3,7\(t0\)
+ 94: a5130009 sh s3,9\(t0\)
+ 98: a1130010 sb s3,16\(t0\)
+ 9c: 0000000d break
+ a0: a1130006 sb s3,6\(t0\)
+ a4: a5130009 sh s3,9\(t0\)
+ a8: 00000000 nop
+ ac: a1130010 sb s3,16\(t0\)
+ b0: 0000000d break
+ b4: a1130007 sb s3,7\(t0\)
+ b8: f5000008 sdc1 \$f0,8\(t0\)
+ bc: a113000f sb s3,15\(t0\)
+ c0: 0000000d break
+ c4: a1130007 sb s3,7\(t0\)
+ c8: f5000008 sdc1 \$f0,8\(t0\)
+ cc: 00000000 nop
+ d0: a1130010 sb s3,16\(t0\)
+ d4: 0000000d break
+ d8: a1130010 sb s3,16\(t0\)
+ dc: f5000008 sdc1 \$f0,8\(t0\)
+ e0: a1130017 sb s3,23\(t0\)
+ e4: 0000000d break
+ e8: a1130010 sb s3,16\(t0\)
+ ec: f5000008 sdc1 \$f0,8\(t0\)
+ f0: 00000000 nop
+ f4: a1130018 sb s3,24\(t0\)
+ f8: 0000000d break
+ fc: a1130008 sb s3,8\(t0\)
+ 100: f5000009 sdc1 \$f0,9\(t0\)
+ 104: a1130010 sb s3,16\(t0\)
+ 108: 0000000d break
+ 10c: a113fffd sb s3,-3\(t0\)
+ 110: f500fffe sdc1 \$f0,-2\(t0\)
+ 114: 00000000 nop
+ 118: a1130006 sb s3,6\(t0\)
+ 11c: 0000000d break
+ ...
--- /dev/null
+ # range check
+ sb $s3,4($t0)
+ sw $s3,8($t0)
+ sb $s3,15($t0)
+ break
+
+ sb $s3,3($t0)
+ sw $s3,8($t0)
+ sb $s3,15($t0)
+ break
+
+ # overlap (same word)
+ sw $s3,28($t0)
+ sw $s3,8($t0)
+ sb $s3,31($t0)
+ break
+
+ # unaligned
+ sb $s3,5($t0)
+ sw $s3,9($t0)
+ sb $s3,16($t0)
+ break
+
+ sb $s3,4($t0)
+ sw $s3,9($t0)
+ sb $s3,16($t0)
+ break
+
+ # range check
+ sb $s3,6($t0)
+ sh $s3,8($t0)
+ sb $s3,15($t0)
+ break
+
+ sb $s3,5($t0)
+ sh $s3,8($t0)
+ sb $s3,15($t0)
+ break
+
+ # overlap (same hword)
+ sh $s3,30($t0)
+ sh $s3,8($t0)
+ sb $s3,31($t0)
+ break
+
+ # unaligned
+ sb $s3,7($t0)
+ sh $s3,9($t0)
+ sb $s3,16($t0)
+ break
+
+ sb $s3,6($t0)
+ sh $s3,9($t0)
+ sb $s3,16($t0)
+ break
+
+ # range check
+ sb $s3,7($t0)
+ sdc1 $f0,8($t0)
+ sb $s3,15($t0)
+ break
+
+ sb $s3,7($t0)
+ sdc1 $f0,8($t0)
+ sb $s3,16($t0)
+ break
+
+ # overlap (same dword)
+ sb $s3,16($t0)
+ sdc1 $f0,8($t0)
+ sb $s3,23($t0)
+ break
+
+ sb $s3,16($t0)
+ sdc1 $f0,8($t0)
+ sb $s3,24($t0)
+ break
+
+ # unaligned
+ sb $s3,8($t0)
+ sdc1 $f0,9($t0)
+ sb $s3,16($t0)
+ break
+
+ sb $s3,-3($t0)
+ sdc1 $f0,-2($t0)
+ sb $s3,6($t0)
+ break
+
+# Force at least 8 (non-delay-slot) zero bytes,to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple Store (Range Check >= 24)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+ 0: a1130000 sb s3,0\(t0\)
+ 4: 00000000 nop
+ 8: a1130001 sb s3,1\(t0\)
+ c: a1130018 sb s3,24\(t0\)
+ 10: 0000000d break
+ 14: a1130000 sb s3,0\(t0\)
+ 18: a1130001 sb s3,1\(t0\)
+ 1c: a1130019 sb s3,25\(t0\)
+ 20: 0000000d break
+ 24: a1130001 sb s3,1\(t0\)
+ 28: a1130019 sb s3,25\(t0\)
+ 2c: a113001a sb s3,26\(t0\)
+ 30: 0000000d break
+ 34: a1130000 sb s3,0\(t0\)
+ 38: a5130003 sh s3,3\(t0\)
+ 3c: 00000000 nop
+ 40: a113001a sb s3,26\(t0\)
+ 44: 0000000d break
+ 48: a5130000 sh s3,0\(t0\)
+ 4c: a1130003 sb s3,3\(t0\)
+ 50: a113001a sb s3,26\(t0\)
+ 54: 0000000d break
+ 58: a1130023 sb s3,35\(t0\)
+ 5c: a5130020 sh s3,32\(t0\)
+ 60: a1130009 sb s3,9\(t0\)
+ 64: 0000000d break
+ 68: a1130001 sb s3,1\(t0\)
+ 6c: a5130019 sh s3,25\(t0\)
+ 70: a113001b sb s3,27\(t0\)
+ 74: 0000000d break
+ 78: a1130000 sb s3,0\(t0\)
+ 7c: ad130007 sw s3,7\(t0\)
+ 80: 00000000 nop
+ 84: a113001c sb s3,28\(t0\)
+ 88: 0000000d break
+ 8c: a1130000 sb s3,0\(t0\)
+ 90: a1130007 sb s3,7\(t0\)
+ 94: ad13001c sw s3,28\(t0\)
+ 98: 0000000d break
+ 9c: a1130040 sb s3,64\(t0\)
+ a0: ad13003b sw s3,59\(t0\)
+ a4: 00000000 nop
+ a8: ad130025 sw s3,37\(t0\)
+ ac: 0000000d break
+ b0: ad130040 sw s3,64\(t0\)
+ b4: a113003d sb s3,61\(t0\)
+ b8: a1130027 sb s3,39\(t0\)
+ bc: 0000000d break
+ c0: a1130001 sb s3,1\(t0\)
+ c4: ad130019 sw s3,25\(t0\)
+ c8: a113001d sb s3,29\(t0\)
+ cc: 0000000d break
+ \.\.\.
--- /dev/null
+ # Range check after alignment between adjacent offsets >= 24 ??
+
+ sb $s3,0($t0)
+ sb $s3,1($t0)
+ sb $s3,24($t0)
+ break
+ sb $s3,0($t0)
+ sb $s3,1($t0)
+ sb $s3,25($t0)
+ break
+ sb $s3,1($t0)
+ sb $s3,25($t0)
+ sb $s3,26($t0)
+ break
+
+ sb $s3,0($t0)
+ sh $s3,3($t0)
+ sb $s3,26($t0)
+ break
+ sh $s3,0($t0)
+ sb $s3,3($t0)
+ sb $s3,26($t0)
+ break
+ sb $s3,35($t0)
+ sh $s3,32($t0)
+ sb $s3,9($t0)
+ break
+ sb $s3,1($t0)
+ sh $s3,25($t0)
+ sb $s3,27($t0)
+ break
+
+ sb $s3,0($t0)
+ sw $s3,7($t0)
+ sb $s3,28($t0)
+ break
+ sb $s3,0($t0)
+ sb $s3,7($t0)
+ sw $s3,28($t0)
+ break
+ sb $s3,64($t0)
+ sw $s3,59($t0)
+ sw $s3,37($t0)
+ break
+ sw $s3,64($t0)
+ sb $s3,61($t0)
+ sb $s3,39($t0)
+ break
+ sb $s3,1($t0)
+ sw $s3,25($t0)
+ sb $s3,29($t0)
+ break
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
--- /dev/null
+#objdump: -dr
+#as: -mfix-24k
+#name: 24K: Triple store (Intervening data #1)
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: a1020000 sb v0,0\(t0\)
+ 4: 00000000 nop
+ 8: a1030008 sb v1,8\(t0\)
+ c: a1040010 sb a0,16\(t0\)
--- /dev/null
+ .text
+ sb $2,0($8)
+ .data
+ .word 1
+ .text
+ sb $3,8($8)
+ .data
+ .word 1
+ .text
+ sb $4,16($8)
run_dump_test "eret-1"
run_dump_test "eret-2"
run_dump_test "eret-3"
+ run_dump_test_arches "24k-branch-delay-1" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-triple-stores-1" \
+ [mips_arch_list_matching mips32r2 !octeon]
+ run_dump_test_arches "24k-triple-stores-2" [mips_arch_list_matching mips2]
+ run_dump_test_arches "24k-triple-stores-3" [mips_arch_list_matching mips3]
+ run_dump_test_arches "24k-triple-stores-4" [mips_arch_list_matching mips2]
+ run_dump_test_arches "24k-triple-stores-5" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-triple-stores-6" [mips_arch_list_matching mips2]
+ run_dump_test_arches "24k-triple-stores-7" [mips_arch_list_matching mips2]
+ run_dump_test_arches "24k-triple-stores-8" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-triple-stores-9" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-triple-stores-10" [mips_arch_list_matching mips1]
+ run_dump_test_arches "24k-triple-stores-11" [mips_arch_list_matching mips1]
if $elf {
run_dump_test_arches "jal-svr4pic" \
projects / external / binutils.git / commitdiff