[X86] Use instrs instead of instregex for gather/scatter instructions in the schedule...

The reduces the number of scheduler groups in subtarget info.

llvm-svn: 320923

diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 8319dbc..1423014 100755 (executable)
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -3710,50 +3710,50 @@ def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156
   let NumMicroOps = 7;
   let ResourceCycles = [1,3,2,1];
 }
-def: InstRW<[BWWriteResGroup183_1], (instregex "VGATHERQPDrm")>;
+def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
 
 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 23;
   let NumMicroOps = 9;
   let ResourceCycles = [1,3,4,1];
 }
-def: InstRW<[BWWriteResGroup183_2], (instregex "VGATHERQPDYrm")>;
+def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
 
 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
   let ResourceCycles = [1,5,2,1];
 }
-def: InstRW<[BWWriteResGroup183_3], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
 
 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 25;
   let NumMicroOps = 7;
   let ResourceCycles = [1,3,2,1];
 }
-def: InstRW<[BWWriteResGroup183_4], (instregex "VGATHERDPDrm")>;
-def: InstRW<[BWWriteResGroup183_4], (instregex "VGATHERDPSrm")>;
+def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
+                                            VGATHERDPSrm)>;
 
 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 26;
   let NumMicroOps = 9;
   let ResourceCycles = [1,5,2,1];
 }
-def: InstRW<[BWWriteResGroup183_5], (instregex "VGATHERDPDYrm")>;
+def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
 
 def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 26;
   let NumMicroOps = 14;
   let ResourceCycles = [1,4,8,1];  
 }
-def: InstRW<[BWWriteResGroup183_6], (instregex "VGATHERDPSYrm")>;
+def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
 
 def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 27;
   let NumMicroOps = 9;
   let ResourceCycles = [1,5,2,1];
 }
-def: InstRW<[BWWriteResGroup183_7], (instregex "VGATHERQPSrm")>;
+def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
 
 def BWWriteResGroup184 : SchedWriteRes<[BWPort0,BWPort5,BWPort015]> {
   let Latency = 29;

diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index c1c09cc..4c27e08 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -4319,69 +4319,69 @@ def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, H
   let NumMicroOps = 12;
   let ResourceCycles = [2,2,1,3,2,2];
 }
-def: InstRW<[HWWriteResGroup184], (instregex "VGATHERDPDrm")>;
-def: InstRW<[HWWriteResGroup184], (instregex "VPGATHERDQrm")>;
-def: InstRW<[HWWriteResGroup184], (instregex "VPGATHERDDrm")>;
+def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm,
+                                          VPGATHERDQrm,
+                                          VPGATHERDDrm)>;
 
 def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 24;
   let NumMicroOps = 22;
   let ResourceCycles = [5,3,4,1,5,4];
 }
-def: InstRW<[HWWriteResGroup185], (instregex "VGATHERQPDYrm")>;
-def: InstRW<[HWWriteResGroup185], (instregex "VPGATHERQQYrm")>;
+def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm,
+                                          VPGATHERQQYrm)>;
 
 def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 28;
   let NumMicroOps = 22;
   let ResourceCycles = [5,3,4,1,5,4];
 }
-def: InstRW<[HWWriteResGroup186], (instregex "VPGATHERQDYrm")>;
+def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>;
 
 def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 25;
   let NumMicroOps = 22;
   let ResourceCycles = [5,3,4,1,5,4];
 }
-def: InstRW<[HWWriteResGroup187], (instregex "VPGATHERQDrm")>;
+def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>;
 
 def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 27;
   let NumMicroOps = 20;
   let ResourceCycles = [3,3,4,1,5,4];
 }
-def: InstRW<[HWWriteResGroup188], (instregex "VGATHERDPDYrm")>;
-def: InstRW<[HWWriteResGroup188], (instregex "VPGATHERDQYrm")>;
+def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm,
+                                          VPGATHERDQYrm)>;
 
 def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 27;
   let NumMicroOps = 34;
   let ResourceCycles = [5,3,8,1,9,8];
 }
-def: InstRW<[HWWriteResGroup189], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[HWWriteResGroup189], (instregex "VPGATHERDDYrm")>;
+def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm,
+                                          VPGATHERDDYrm)>;
 
 def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 23;
   let NumMicroOps = 14;
   let ResourceCycles = [3,3,2,1,3,2];
 }
-def: InstRW<[HWWriteResGroup190], (instregex "VGATHERQPDrm")>;
-def: InstRW<[HWWriteResGroup190], (instregex "VPGATHERQQrm")>;
+def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm,
+                                          VPGATHERQQrm)>;
 
 def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 28;
   let NumMicroOps = 15;
   let ResourceCycles = [3,3,2,1,4,2];
 }
-def: InstRW<[HWWriteResGroup191], (instregex "VGATHERQPSYrm")>;
+def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>;
 
 def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> {
   let Latency = 25;
   let NumMicroOps = 15;
   let ResourceCycles = [3,3,2,1,4,2];
 }
-def: InstRW<[HWWriteResGroup192], (instregex "VGATHERQPSrm")>;
-def: InstRW<[HWWriteResGroup192], (instregex "VGATHERDPSrm")>;
+def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm,
+                                          VGATHERDPSrm)>;
 
 } // SchedModel

diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index bc9ca7e..8a0a261 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -3786,42 +3786,28 @@ def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPor
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKLWriteResGroup196_1], (instregex "VGATHERQPDrm")>;
+def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
+                                             VGATHERDPDrm,
+                                             VGATHERQPDrm,
+                                             VGATHERQPSrm,
+                                             VPGATHERDDrm,
+                                             VPGATHERDQrm,
+                                             VPGATHERQDrm,
+                                             VPGATHERQQrm)>;
 
 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
   let Latency = 25;
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPDYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKLWriteResGroup196_2], (instregex "VGATHERDPDYrm")>;
+def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
+                                             VGATHERQPDYrm,
+                                             VGATHERQPSYrm,
+                                             VPGATHERDDYrm,
+                                             VPGATHERDQYrm,
+                                             VPGATHERQDYrm,
+                                             VPGATHERQQYrm,
+                                             VGATHERDPDYrm)>;
 
 def SKLWriteResGroup197 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 23;

diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 46ac7e7..1376f7b 100755 (executable)
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -4055,10 +4055,10 @@ def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort015
   let NumMicroOps = 7;
   let ResourceCycles = [1,2,2,2];
 }
-def: InstRW<[SKXWriteResGroup110], (instregex "VPSCATTERDQZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup110], (instregex "VPSCATTERQQZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup110], (instregex "VSCATTERDPDZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup110], (instregex "VSCATTERQPDZ128mr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
+                                           VPSCATTERQQZ128mr,
+                                           VSCATTERDPDZ128mr,
+                                           VSCATTERQPDZ128mr)>;
 
 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
   let Latency = 7;
@@ -4072,27 +4072,27 @@ def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort015
   let NumMicroOps = 11;
   let ResourceCycles = [1,4,4,2];
 }
-def: InstRW<[SKXWriteResGroup112], (instregex "VPSCATTERDQZ256mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup112], (instregex "VPSCATTERQQZ256mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup112], (instregex "VSCATTERDPDZ256mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup112], (instregex "VSCATTERQPDZ256mr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
+                                           VPSCATTERQQZ256mr,
+                                           VSCATTERDPDZ256mr,
+                                           VSCATTERQPDZ256mr)>;
 
 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 19;
   let ResourceCycles = [1,8,8,2];
 }
-def: InstRW<[SKXWriteResGroup113], (instregex "VPSCATTERDQZmr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup113], (instregex "VPSCATTERQQZmr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup113], (instregex "VSCATTERDPDZmr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup113], (instregex "VSCATTERQPDZmr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
+                                           VPSCATTERQQZmr,
+                                           VSCATTERDPDZmr,
+                                           VSCATTERQPDZmr)>;
 
 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 7;
   let NumMicroOps = 36;
   let ResourceCycles = [1,16,1,16,2];
 }
-def: InstRW<[SKXWriteResGroup114], (instregex "VSCATTERDPSZmr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
 
 def SKXWriteResGroup115 : SchedWriteRes<[SKXPort0]> {
   let Latency = 8;
@@ -4725,33 +4725,33 @@ def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,S
   let NumMicroOps = 8;
   let ResourceCycles = [1,2,1,2,2];
 }
-def: InstRW<[SKXWriteResGroup131], (instregex "VPSCATTERQDZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup131], (instregex "VPSCATTERQDZ256mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup131], (instregex "VSCATTERQPSZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup131], (instregex "VSCATTERQPSZ256mr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
+                                           VPSCATTERQDZ256mr,
+                                           VSCATTERQPSZ128mr,
+                                           VSCATTERQPSZ256mr)>;
 
 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 12;
   let ResourceCycles = [1,4,1,4,2];
 }
-def: InstRW<[SKXWriteResGroup132], (instregex "VPSCATTERDDZ128mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup132], (instregex "VSCATTERDPSZ128mr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
+                                           VSCATTERDPSZ128mr)>;
 
 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 20;
   let ResourceCycles = [1,8,1,8,2];
 }
-def: InstRW<[SKXWriteResGroup133], (instregex "VPSCATTERDDZ256mr(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup133], (instregex "VSCATTERDPSZ256mr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
+                                           VSCATTERDPSZ256mr)>;
 
 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
   let NumMicroOps = 36;
   let ResourceCycles = [1,16,1,16,2];
 }
-def: InstRW<[SKXWriteResGroup134], (instregex "VPSCATTERDDZmr(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
 
 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 9;
@@ -6067,9 +6067,9 @@ def SKXWriteResGroup214 : SchedWriteRes<[]> {
   let Latency = 20;
   let NumMicroOps = 0;
 }
-def: InstRW<[SKXWriteResGroup214], (instregex "VGATHERDPSZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup214], (instregex "VGATHERQPSZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup214], (instregex "VPGATHERDDZ128rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
+                                           VGATHERQPSZrm,
+                                           VPGATHERDDZ128rm)>;
 
 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
   let Latency = 20;
@@ -6102,10 +6102,10 @@ def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup218], (instregex "VGATHERQPSZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup218], (instregex "VGATHERQPSZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup218], (instregex "VPGATHERQDZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup218], (instregex "VPGATHERQDZ256rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
+                                           VGATHERQPSZ256rm,
+                                           VPGATHERQDZ128rm,
+                                           VPGATHERQDZ256rm)>;
 
 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
   let Latency = 20;
@@ -6152,52 +6152,52 @@ def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup224], (instregex "VGATHERDPDZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup224], (instregex "VGATHERQPDZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup224], (instregex "VPGATHERDQZ128rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup224], (instregex "VPGATHERQQZ128rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
+                                           VGATHERQPDZ128rm,
+                                           VPGATHERDQZ128rm,
+                                           VPGATHERQQZ128rm)>;
 
 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
   let Latency = 22;
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERQPDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERDDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERQDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERDQrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VPGATHERQQrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERDPSrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERQPSrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERDPDrm")>;
-def: InstRW<[SKXWriteResGroup224_2], (instregex "VGATHERQPDrm")>;
+def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
+                                             VGATHERDPDrm,
+                                             VGATHERQPDrm,
+                                             VGATHERQPSrm,
+                                             VPGATHERDDrm,
+                                             VPGATHERDQrm,
+                                             VPGATHERQDrm,
+                                             VPGATHERQQrm,
+                                             VPGATHERDDrm,
+                                             VPGATHERQDrm,
+                                             VPGATHERDQrm,
+                                             VPGATHERQQrm,
+                                             VGATHERDPSrm,
+                                             VGATHERQPSrm,
+                                             VGATHERDPDrm,
+                                             VGATHERQPDrm)>;
 
 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
   let Latency = 25;
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERQPDYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERDDYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERQDYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERDQYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VPGATHERQQYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERDPSYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERQPSYrm")>;
-def: InstRW<[SKXWriteResGroup224_3], (instregex "VGATHERDPDYrm")>;
+def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
+                                             VGATHERQPDYrm,
+                                             VGATHERQPSYrm,
+                                             VPGATHERDDYrm,
+                                             VPGATHERDQYrm,
+                                             VPGATHERQDYrm,
+                                             VPGATHERQQYrm,
+                                             VPGATHERDDYrm,
+                                             VPGATHERQDYrm,
+                                             VPGATHERDQYrm,
+                                             VPGATHERQQYrm,
+                                             VGATHERDPSYrm,
+                                             VGATHERQPSYrm,
+                                             VGATHERDPDYrm)>;
 
 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
   let Latency = 22;
@@ -6276,11 +6276,11 @@ def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup234], (instregex "VGATHERDPDZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup234], (instregex "VGATHERQPDZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup234], (instregex "VPGATHERDQZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup234], (instregex "VPGATHERQDZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup234], (instregex "VPGATHERQQZ256rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
+                                           VGATHERQPDZ256rm,
+                                           VPGATHERDQZ256rm,
+                                           VPGATHERQDZrm,
+                                           VPGATHERQQZ256rm)>;
 
 def SKXWriteResGroup235 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015,SKXPort0156]> {
   let Latency = 25;
@@ -6310,10 +6310,10 @@ def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup238], (instregex "VGATHERDPDZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup238], (instregex "VGATHERQPDZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup238], (instregex "VPGATHERDQZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup238], (instregex "VPGATHERQQZrm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
+                                           VGATHERQPDZrm,
+                                           VPGATHERDQZrm,
+                                           VPGATHERQQZrm)>;
 
 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
   let Latency = 27;
@@ -6328,8 +6328,8 @@ def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup240], (instregex "VGATHERDPSZ256rm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup240], (instregex "VPGATHERDDZ256rm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
+                                           VPGATHERDDZ256rm)>;
 
 def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> {
   let Latency = 28;
@@ -6366,8 +6366,8 @@ def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort01
   let NumMicroOps = 5;
   let ResourceCycles = [1,2,1,1];
 }
-def: InstRW<[SKXWriteResGroup245], (instregex "VGATHERDPSZrm(b?)(k?)(z?)")>;
-def: InstRW<[SKXWriteResGroup245], (instregex "VPGATHERDDZrm(b?)(k?)(z?)")>;
+def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
+                                           VPGATHERDDZrm)>;
 
 def SKXWriteResGroup246 : SchedWriteRes<[SKXPort0,SKXPort015]> {
   let Latency = 31;