clk: imx: Rename sccg and frac pll register to suggest clk_hw
authorAbel Vesa <abel.vesa@nxp.com>
Wed, 11 Dec 2019 09:25:46 +0000 (11:25 +0200)
committerShawn Guo <shawnguo@kernel.org>
Wed, 11 Dec 2019 11:19:50 +0000 (19:19 +0800)
Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to
imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious
that they are clk_hw based.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-frac-pll.c
drivers/clk/imx/clk-sscg-pll.c
drivers/clk/imx/clk.h

index fece503..101e0a3 100644 (file)
@@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops = {
        .set_rate       = clk_pll_set_rate,
 };
 
-struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
-                            void __iomem *base)
+struct clk_hw *imx_clk_hw_frac_pll(const char *name,
+                                  const char *parent_name,
+                                  void __iomem *base)
 {
        struct clk_init_data init;
        struct clk_frac_pll *pll;
@@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
                return ERR_PTR(ret);
        }
 
-       return hw->clk;
+       return hw;
 }
index 0669e17..acd1b90 100644 (file)
@@ -506,7 +506,7 @@ static const struct clk_ops clk_sscg_pll_ops = {
        .determine_rate = clk_sscg_pll_determine_rate,
 };
 
-struct clk *imx_clk_sscg_pll(const char *name,
+struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
                                const char * const *parent_names,
                                u8 num_parents,
                                u8 parent, u8 bypass1, u8 bypass2,
@@ -545,5 +545,5 @@ struct clk *imx_clk_sscg_pll(const char *name,
                return ERR_PTR(ret);
        }
 
-       return hw->clk;
+       return hw;
 }
index 8ffdaca..23c73a2 100644 (file)
@@ -116,6 +116,14 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
 #define imx_clk_pllv2(name, parent, base) \
        to_clk(imx_clk_hw_pllv2(name, parent, base))
 
+#define imx_clk_frac_pll(name, parent_name, base) \
+       to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
+
+#define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
+                               bypass1, bypass2, base, flags) \
+       to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
+                               bypass1, bypass2, base, flags))
+
 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
                 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
 
@@ -125,10 +133,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
                void __iomem *base);
 
-struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
+struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
                             void __iomem *base);
 
-struct clk *imx_clk_sscg_pll(const char *name,
+struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
                                const char * const *parent_names,
                                u8 num_parents,
                                u8 parent, u8 bypass1, u8 bypass2,