+2006-06-09 Thiemo Seufer <ths@mips.com>
+
+ * config/tc-mips.c (mips_ip): Maintain argument count.
+
2006-06-09 Alan Modra <amodra@bigpond.net.au>
* config/tc-iq2000.c: Include sb.h.
+2006-06-09 Thiemo Seufer <ths@mips.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * gas/mips/mips32-sf32.s, gas/mips/mips32-sf32.d: New test for odd
+ single precision FPRs on MIPS32.
+ * gas/mips/mips.exp: Run them.
+
2006-06-08 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
run_dump_test_arches "mips32" [mips_arch_list_matching mips32]
+ run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32]
+
run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2]
run_list_test_arches "mips32r2-ill" "-32" \
[mips_arch_list_matching mips32r2 gpr32]
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS32 odd single-precision float registers
+#as: -32
+
+# Check MIPS32 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 3c013f80 lui \$1,0x3f80
+0+0004 <[^>]*> 44810800 mtc1 \$1,\$f1
+0+0008 <[^>]*> c783c000 lwc1 \$f3,-16384\(\$28\)
+ 8: R_MIPS_LITERAL \.lit4\+0x4000
+0+000c <[^>]*> 46030940 add.s \$f5,\$f1,\$f3
+0+0010 <[^>]*> 46003a21 cvt.d.s \$f8,\$f7
+0+0014 <[^>]*> 46803a21 cvt.d.w \$f8,\$f7
+0+0018 <[^>]*> 462041e0 cvt.s.d \$f7,\$f8
+0+001c <[^>]*> 462041cd trunc.w.d \$f7,\$f8
+ \.\.\.