cap-mmc-dual-data-rate;
};
+&dss {
+ status = "ok";
+
+ vdda_video-supply = <&ldoln_reg>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins &i2c2_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
++
+ &mailbox5 {
+ status = "okay";
+ mbox_ipu1_legacy: mbox_ipu1_legacy {
+ status = "okay";
+ };
+ mbox_dsp1_legacy: mbox_dsp1_legacy {
+ status = "okay";
+ };
+ };
+
+ &mailbox6 {
+ status = "okay";
+ mbox_ipu2_legacy: mbox_ipu2_legacy {
+ status = "okay";
+ };
+ mbox_dsp2_legacy: mbox_dsp2_legacy {
+ status = "okay";
+ };
+ };
+
+ &mmu0_dsp1 {
+ status = "okay";
+ };
+
+ &mmu1_dsp1 {
+ status = "okay";
+ };
+
+ &mmu0_dsp2 {
+ status = "okay";
+ };
+
+ &mmu1_dsp2 {
+ status = "okay";
+ };
+
+ &mmu_ipu1 {
+ status = "okay";
+ };
+
+ &mmu_ipu2 {
+ status = "okay";
+ };
+
+ &ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_cma_pool>;
+ mboxes = <&mailbox6 &mbox_ipu2_legacy>;
+ timers = <&timer3>;
+ watchdog-timers = <&timer4>, <&timer9>;
+ };
+
+ &ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_ipu1_legacy>;
+ timers = <&timer11>;
+ };
+
+ &dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_dsp1_legacy>;
+ timers = <&timer5>;
+ };
+
+ &dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_cma_pool>;
+ mboxes = <&mailbox6 &mbox_dsp2_legacy>;
+ timers = <&timer6>;
+ };
ti,no-idle-on-init;
};
+&dss {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &vout1_pins
+ &hpd_pin
+ >;
+
+ vdda_video-supply = <&ldoln_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ reg = <0>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&tlc_in>;
+ data-lines = <24>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcan1_pins_default>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+};
++
+ &mailbox5 {
+ status = "okay";
+ mbox_ipu1_legacy: mbox_ipu1_legacy {
+ status = "okay";
+ };
+ mbox_dsp1_legacy: mbox_dsp1_legacy {
+ status = "okay";
+ };
+ };
+
+ &mailbox6 {
+ status = "okay";
+ mbox_ipu2_legacy: mbox_ipu2_legacy {
+ status = "okay";
+ };
+ mbox_dsp2_legacy: mbox_dsp2_legacy {
+ status = "okay";
+ };
+ };
+
+ &mmu0_dsp1 {
+ status = "okay";
+ };
+
+ &mmu1_dsp1 {
+ status = "okay";
+ };
+
+ &mmu0_dsp2 {
+ status = "okay";
+ };
+
+ &mmu1_dsp2 {
+ status = "okay";
+ };
+
+ &mmu_ipu1 {
+ status = "okay";
+ };
+
+ &mmu_ipu2 {
+ status = "okay";
+ };
+
+ &ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_cma_pool>;
+ mboxes = <&mailbox6 &mbox_ipu2_legacy>;
+ timers = <&timer3>;
+ watchdog-timers = <&timer4>, <&timer9>;
+ };
+
+ &ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_ipu1_legacy>;
+ timers = <&timer11>;
+ };
+
+ &dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_dsp1_legacy>;
+ timers = <&timer5>;
+ };
+
+ &dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_cma_pool>;
+ mboxes = <&mailbox6 &mbox_dsp2_legacy>;
+ timers = <&timer6>;
+ };
reg = <0x80000000 0x40000000>; /* 1024 MB */
};
+ tpd12s015: encoder@0 {
+ compatible = "omapdss,ti,tpd12s015";
+
+ gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
+ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ hdmi0: connector@0 {
+ compatible = "omapdss,hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ipu2_cma_pool: ipu2_cma@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x95800000 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_cma_pool: dsp1_cma@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x99000000 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_cma_pool: ipu1_cma@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x9d000000 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
mmc2_3v3: fixedregulator-mmc2 {
compatible = "regulator-fixed";
regulator-name = "mmc2_3v3";
ti,non-removable;
};
+&mac {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <3>;
+ phy-mode = "rgmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
+&cpu0 {
+ cpu0-voltdm = <&voltdm_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&voltdm_mpu {
+ vdd-supply = <&smps1_reg>;
+};
+
+&voltdm_core {
+ vdd-supply = <&smps2_reg>;
+};
+
+&voltdm_dspeve {
+ vdd-supply = <&smps3_reg>;
+};
+
+&voltdm_gpu {
+ vdd-supply = <&smps3_reg>;
+};
+
+&voltdm_ivahd {
+ vdd-supply = <&smps3_reg>;
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_default>;
+ ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ nand@0,0 {
+ /* To use NAND, DIP switch SW5 must be set like so:
+ * SW5.1 (NAND_SELn) = ON (LOW)
+ * SW5.9 (GPMC_WPN) = OFF (HIGH)
+ */
+ reg = <0 0 4>; /* device IO registers */
+ ti,nand-ecc-opt = "bch8";
+ ti,elm-id = <&elm>;
+ nand-bus-width = <16>;
+ gpmc,device-width = <2>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <80>;
+ gpmc,cs-wr-off-ns = <80>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <60>;
+ gpmc,adv-wr-off-ns = <60>;
+ gpmc,we-on-ns = <10>;
+ gpmc,we-off-ns = <50>;
+ gpmc,oe-on-ns = <4>;
+ gpmc,oe-off-ns = <40>;
+ gpmc,access-ns = <40>;
+ gpmc,wr-access-ns = <80>;
+ gpmc,rd-cycle-ns = <80>;
+ gpmc,wr-cycle-ns = <80>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+ * which can be independently programmable. For
+ * NAND flash this is equal to size of erase-block */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "NAND.SPL";
+ reg = <0x00000000 0x000020000>;
+ };
+ partition@1 {
+ label = "NAND.SPL.backup1";
+ reg = <0x00020000 0x00020000>;
+ };
+ partition@2 {
+ label = "NAND.SPL.backup2";
+ reg = <0x00040000 0x00020000>;
+ };
+ partition@3 {
+ label = "NAND.SPL.backup3";
+ reg = <0x00060000 0x00020000>;
+ };
+ partition@4 {
+ label = "NAND.u-boot-spl-os";
+ reg = <0x00080000 0x00040000>;
+ };
+ partition@5 {
+ label = "NAND.u-boot";
+ reg = <0x000c0000 0x00100000>;
+ };
+ partition@6 {
+ label = "NAND.u-boot-env";
+ reg = <0x001c0000 0x00020000>;
+ };
+ partition@7 {
+ label = "NAND.u-boot-env.backup1";
+ reg = <0x001e0000 0x00020000>;
+ };
+ partition@8 {
+ label = "NAND.kernel";
+ reg = <0x00200000 0x00800000>;
+ };
+ partition@9 {
+ label = "NAND.file-system";
+ reg = <0x00a00000 0x0f600000>;
+ };
+ };
+};
+
+&dss {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vout1_pins>;
+
+ vdda-supply = <&ldo5_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ reg = <0>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&tlc_in>;
+ data-lines = <24>;
+ };
+ };
+ };
+};
+
+
+&dcan1 {
+ status = "ok";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcan1_pins_default>;
+ pinctrl-1 = <&dcan1_pins_sleep>;
+};
+
+&hdmi {
+ status = "ok";
+ vdda-supply = <&ldo3_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hpd_pin &i2c2_pins>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
++
+ &mailbox5 {
+ status = "okay";
+ mbox_ipu1_legacy: mbox_ipu1_legacy {
+ status = "okay";
+ };
+ mbox_dsp1_legacy: mbox_dsp1_legacy {
+ status = "okay";
+ };
+ };
+
+ &mailbox6 {
+ status = "okay";
+ mbox_ipu2_legacy: mbox_ipu2_legacy {
+ status = "okay";
+ };
+ };
+
+ &mmu0_dsp1 {
+ status = "okay";
+ };
+
+ &mmu1_dsp1 {
+ status = "okay";
+ };
+
+ &mmu_ipu1 {
+ status = "okay";
+ };
+
+ &mmu_ipu2 {
+ status = "okay";
+ };
+
+ &ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_cma_pool>;
+ mboxes = <&mailbox6 &mbox_ipu2_legacy>;
+ timers = <&timer3>;
+ watchdog-timers = <&timer4>, <&timer9>;
+ };
+
+ &ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_ipu1_legacy>;
+ timers = <&timer11>;
+ };
+
+ &dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_cma_pool>;
+ mboxes = <&mailbox5 &mbox_dsp1_legacy>;
+ timers = <&timer5>;
+ };
};
};
+ thermal-zones {
+ #include "omap4-cpu-thermal.dtsi"
+ };
+
+ aliases {
+ rproc0 = &ipu1;
+ rproc1 = &ipu2;
+ rproc2 = &dsp1;
+ };
+
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
};
};
++ thermal-zones {
++ #include "omap4-cpu-thermal.dtsi"
++ };
++
+ aliases {
+ rproc0 = &ipu1;
+ rproc1 = &ipu2;
+ rproc2 = &dsp1;
+ rproc3 = &dsp2;
+ };
+
ocp {
- };
+ omap_dwc3_4@48940000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss4";
+ reg = <0x48940000 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb4: usb@48950000 {
+ compatible = "snps,dwc3";
+ reg = <0x48950000 0x17000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
- thermal-zones {
- #include "omap4-cpu-thermal.dtsi"
+
+ mmu0_dsp2: mmu@41501000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x41501000 0x100>, <0x41500000 0x100>;
+ reg-names = "mmu_cfg", "dsp_system";
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu0_dsp2";
+ status = "disabled";
+ };
+
+ mmu1_dsp2: mmu@41502000 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x41502000 0x100>, <0x41500000 0x100>;
+ reg-names = "mmu_cfg", "dsp_system";
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "mmu1_dsp2";
+ status = "disabled";
+ };
+
+ dsp2: dsp@41000000 {
+ compatible = "ti,dra7-rproc-dsp";
+ reg = <0x41000000 0x48000>;
+ reg-names = "l2ram";
+ ti,hwmods = "dsp2";
+ iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
+ status = "disabled";
+ };
};
pmu {
};
&cpu0 {
- cpu0-supply = <&smps123_reg>;
+ cpu0-voltdm = <&voltdm_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&voltdm_mpu {
+ vdd-supply = <&smps123_reg>;
+};
+
+&voltdm_mm {
+ vdd-supply = <&smps45_reg>;
+};
+
+&voltdm_core {
+ vdd-supply = <&smps6_reg>;
};
+ &dsp {
+ status = "okay";
+ memory-region = <&dsp_cma_pool>;
+ timers = <&timer5>;
+ watchdog-timers = <&timer6>;
+ };
+
+ &ipu {
+ status = "okay";
+ memory-region = <&ipu_cma_pool>;
+ timers = <&timer3>;
+ watchdog-timers = <&timer9>, <&timer11>;
+ };
+
&dss {
status = "ok";
};
&dra7xx_l4_per1__mmc2,
&dra7xx_l4_per1__mmc3,
&dra7xx_l4_per1__mmc4,
+ &dra7xx_l3_main_1__mmu0_dsp1,
+ &dra7xx_l3_main_1__mmu1_dsp1,
+ &dra7xx_l3_main_1__mmu_ipu1,
+ &dra7xx_l3_main_1__mmu_ipu2,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l3_main_1__pcie1,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l3_main_1__pcie2,
+ &dra7xx_l4_cfg__pcie2,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_per3__rtcss,
&dra7xx_l4_cfg__sata,
#include <linux/platform_data/pinctrl-single.h>
#include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/wkup_m3.h>
+#include <linux/platform_data/sgx-omap.h>
+#include <linux/platform_data/pci-dra7xx.h>
+ #include <linux/platform_data/remoteproc-omap.h>
#include "am35xx.h"
#include "common.h"
OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
&am35xx_emac_pdata),
#endif
++
+#ifdef CONFIG_SOC_AM33XX
+ OF_DEV_AUXDATA("ti,am3353-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
+ &wkup_m3_data),
+#endif
+#ifdef CONFIG_SOC_AM43XX
+ OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
+ &wkup_m3_data),
+#endif
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
+ OF_DEV_AUXDATA("ti,sgx", 0x56000000, "56000000.sgx",
+ &sgx_pdata),
+#endif
+ #ifdef CONFIG_SOC_AM43XX
+ OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata),
+ #endif
#ifdef CONFIG_ARCH_OMAP4
OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata),
OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
#endif
+ #ifdef CONFIG_SOC_DRA7XX
+ OF_DEV_AUXDATA("ti,dra7-pcie", 0x51000000, "51000000.pcie",
+ &dra7xx_pci_pdata),
+ OF_DEV_AUXDATA("ti,dra7-pcie", 0x51800000, "51800000.pcie",
+ &dra7xx_pci_pdata),
+ OF_DEV_AUXDATA("ti,dra7-padconf", 0x4a003400, "4a003400.pinmux", &pcs_pdata),
+ OF_DEV_AUXDATA("ti,dra7-iommu", 0x40d01000, "40d01000.mmu",
+ &omap4_iommu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-iommu", 0x41501000, "41501000.mmu",
+ &omap4_iommu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu",
+ &omap4_iommu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",
+ &omap4_iommu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-rproc-ipu", 0x55020000, "55020000.ipu",
+ &omap4_ipu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-rproc-ipu", 0x58820000, "58820000.ipu",
+ &omap4_ipu_pdata),
+ OF_DEV_AUXDATA("ti,dra7-rproc-dsp", 0x40800000, "40800000.dsp",
+ &dra7_dsp1_pdata),
+ OF_DEV_AUXDATA("ti,dra7-rproc-dsp", 0x41000000, "41000000.dsp",
+ &dra7_dsp2_pdata),
+ #endif
{ /* sentinel */ },
};
projects / profile / ivi / kernel-x86-ivi.git / commitdiff