irqchip/sun4i: Add a struct to hold global variables

In order to support different chips, IC specific data should be hold in
a struct. This patch moves irq_base and irq_domain global variables to
struct.

Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
index e3e5b91..0c32506 100644 (file)
--- a/drivers/irqchip/irq-sun4i.c
+++ b/drivers/irqchip/irq-sun4i.c
@@ -31,8 +31,12 @@
 #define SUN4I_IRQ_ENABLE_REG(x)                (0x40 + 0x4 * x)
 #define SUN4I_IRQ_MASK_REG(x)          (0x50 + 0x4 * x)
 
-static void __iomem *sun4i_irq_base;
-static struct irq_domain *sun4i_irq_domain;
+struct sun4i_irq_chip_data {
+       void __iomem *irq_base;
+       struct irq_domain *irq_domain;
+};
+
+static struct sun4i_irq_chip_data *irq_ic_data;
 
 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
 
@@ -43,7 +47,7 @@ static void sun4i_irq_ack(struct irq_data *irqd)
        if (irq != 0)
                return; /* Only IRQ 0 / the ENMI needs to be acked */
 
-       writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
+       writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
 }
 
 static void sun4i_irq_mask(struct irq_data *irqd)
@@ -53,9 +57,9 @@ static void sun4i_irq_mask(struct irq_data *irqd)
        int reg = irq / 32;
        u32 val;
 
-       val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+       val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
        writel(val & ~(1 << irq_off),
-              sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+              irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static void sun4i_irq_unmask(struct irq_data *irqd)
@@ -65,9 +69,9 @@ static void sun4i_irq_unmask(struct irq_data *irqd)
        int reg = irq / 32;
        u32 val;
 
-       val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+       val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
        writel(val | (1 << irq_off),
-              sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+              irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
 }
 
 static struct irq_chip sun4i_irq_chip = {
@@ -95,35 +99,41 @@ static const struct irq_domain_ops sun4i_irq_ops = {
 static int __init sun4i_of_init(struct device_node *node,
                                struct device_node *parent)
 {
-       sun4i_irq_base = of_iomap(node, 0);
-       if (!sun4i_irq_base)
+       irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL);
+       if (!irq_ic_data) {
+               pr_err("kzalloc failed!\n");
+               return -ENOMEM;
+       }
+
+       irq_ic_data->irq_base = of_iomap(node, 0);
+       if (!irq_ic_data->irq_base)
                panic("%pOF: unable to map IC registers\n",
                        node);
 
        /* Disable all interrupts */
-       writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
-       writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
-       writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2));
 
        /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
-       writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
-       writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
-       writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1));
+       writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2));
 
        /* Clear all the pending interrupts */
-       writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
-       writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
-       writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
+       writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
+       writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
+       writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
 
        /* Enable protection mode */
-       writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
+       writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
 
        /* Configure the external interrupt source type */
-       writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
+       writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
 
-       sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
+       irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
                                                 &sun4i_irq_ops, NULL);
-       if (!sun4i_irq_domain)
+       if (!irq_ic_data->irq_domain)
                panic("%pOF: unable to create IRQ domain\n", node);
 
        set_handle_irq(sun4i_handle_irq);
@@ -146,13 +156,15 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
         * the extra check in the common case of 1 hapening after having
         * read the vector-reg once.
         */
-       hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+       hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
        if (hwirq == 0 &&
-                 !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
+                 !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) &
+                         BIT(0)))
                return;
 
        do {
-               handle_domain_irq(sun4i_irq_domain, hwirq, regs);
-               hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+               handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
+               hwirq = readl(irq_ic_data->irq_base +
+                               SUN4I_IRQ_VECTOR_REG) >> 2;
        } while (hwirq != 0);
 }