ppc4xx: Add MII mode support to the EMAC RGMII Bridge

This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 4e863dc..26d74d2 100644 (file)
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -465,30 +465,88 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 #if defined(CONFIG_405EX)
 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 {
-       u32 gmiifer = 0;
+       u32 rgmiifer = 0;
 
        /*
-        * Right now only 2*RGMII is supported. Please extend when needed.
-        * sr - 2007-09-19
+        * The 405EX(r)'s RGMII bridge can operate in one of several
+        * modes, only one of which (2 x RGMII) allows the
+        * simultaneous use of both EMACs on the 405EX.
         */
-       switch (1) {
-       case 1:
+
+       switch (CONFIG_EMAC_PHY_MODE) {
+
+       case EMAC_PHY_MODE_NONE:
+               /* No ports */
+               rgmiifer |= RGMII_FER_DIS       << 0;
+               rgmiifer |= RGMII_FER_DIS       << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_NONE;
+               bis->bi_phymode[1] = BI_PHYMODE_NONE;
+               break;
+       case EMAC_PHY_MODE_NONE_RGMII:
+               /* 1 x RGMII port on channel 0 */
+               rgmiifer |= RGMII_FER_RGMII     << 0;
+               rgmiifer |= RGMII_FER_DIS       << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+               bis->bi_phymode[1] = BI_PHYMODE_NONE;
+               break;
+       case EMAC_PHY_MODE_RGMII_NONE:
+               /* 1 x RGMII port on channel 1 */
+               rgmiifer |= RGMII_FER_DIS       << 0;
+               rgmiifer |= RGMII_FER_RGMII     << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_NONE;
+               bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+               break;
+       case EMAC_PHY_MODE_RGMII_RGMII:
                /* 2 x RGMII ports */
-               out_be32((void *)RGMII_FER, 0x00000055);
+               rgmiifer |= RGMII_FER_RGMII     << 0;
+               rgmiifer |= RGMII_FER_RGMII     << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
                bis->bi_phymode[0] = BI_PHYMODE_RGMII;
                bis->bi_phymode[1] = BI_PHYMODE_RGMII;
                break;
-       case 2:
-               /* 2 x SMII ports */
+       case EMAC_PHY_MODE_NONE_GMII:
+               /* 1 x GMII port on channel 0 */
+               rgmiifer |= RGMII_FER_GMII      << 0;
+               rgmiifer |= RGMII_FER_DIS       << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_GMII;
+               bis->bi_phymode[1] = BI_PHYMODE_NONE;
+               break;
+       case EMAC_PHY_MODE_NONE_MII:
+               /* 1 x MII port on channel 0 */
+               rgmiifer |= RGMII_FER_MII       << 0;
+               rgmiifer |= RGMII_FER_DIS       << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_MII;
+               bis->bi_phymode[1] = BI_PHYMODE_NONE;
+               break;
+       case EMAC_PHY_MODE_GMII_NONE:
+               /* 1 x GMII port on channel 1 */
+               rgmiifer |= RGMII_FER_DIS       << 0;
+               rgmiifer |= RGMII_FER_GMII      << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_NONE;
+               bis->bi_phymode[1] = BI_PHYMODE_GMII;
+               break;
+       case EMAC_PHY_MODE_MII_NONE:
+               /* 1 x MII port on channel 1 */
+               rgmiifer |= RGMII_FER_DIS       << 0;
+               rgmiifer |= RGMII_FER_MII       << 4;
+               out_be32((void *)RGMII_FER, rgmiifer);
+               bis->bi_phymode[0] = BI_PHYMODE_NONE;
+               bis->bi_phymode[1] = BI_PHYMODE_MII;
                break;
        default:
                break;
        }
 
        /* Ensure we setup mdio for this devnum and ONLY this devnum */
-       gmiifer = in_be32((void *)RGMII_FER);
-       gmiifer |= (1 << (19-devnum));
-       out_be32((void *)RGMII_FER, gmiifer);
+       rgmiifer = in_be32((void *)RGMII_FER);
+       rgmiifer |= (1 << (19-devnum));
+       out_be32((void *)RGMII_FER, rgmiifer);
 
        return ((int)0x0);
 }

diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index f3d048c..dc246fd 100644 (file)
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -375,6 +375,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_M88E1111_PHY    1
 #define CONFIG_IBM_EMAC4_V4    1
+#define CONFIG_EMAC_PHY_MODE   EMAC_PHY_MODE_RGMII_RGMII
 #define CONFIG_PHY_ADDR                1       /* PHY address, See schematics  */
 
 #define CONFIG_PHY_RESET       1       /* reset phy upon startup       */

diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 65b240e..ab92ae4 100644 (file)
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -223,6 +223,7 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_M88E1111_PHY    1
 #define CONFIG_IBM_EMAC4_V4    1
+#define CONFIG_EMAC_PHY_MODE   EMAC_PHY_MODE_RGMII_RGMII
 #define CONFIG_PHY_ADDR                6       /* PHY address, See schematics  */
 
 #define CONFIG_PHY_RESET       1       /* reset phy upon startup       */

diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 4c97b36..b74c6fc 100644 (file)
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -153,6 +153,20 @@ typedef struct emac_4xx_hw_st {
 #define SDR0_PFC1_EM_1000      (0x00200000)
 #endif
 
+/*
+ * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
+ * not have a pin function control (PFC) register to otherwise determine
+ * the bridge configuration.
+ */
+#define EMAC_PHY_MODE_NONE             0
+#define EMAC_PHY_MODE_NONE_RGMII       1
+#define EMAC_PHY_MODE_RGMII_NONE       2
+#define EMAC_PHY_MODE_RGMII_RGMII      3
+#define EMAC_PHY_MODE_NONE_GMII                4
+#define EMAC_PHY_MODE_GMII_NONE                5
+#define EMAC_PHY_MODE_NONE_MII         6
+#define EMAC_PHY_MODE_MII_NONE         7
+
 /* ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st {
 #endif
 
 /* RGMII Function Enable (FER) Register Bit Definitions */
-/* Note: for EMAC 2 and 3 only, 440GX only */
 #define RGMII_FER_DIS          (0x00)
 #define RGMII_FER_RTBI         (0x04)
 #define RGMII_FER_RGMII                (0x05)
 #define RGMII_FER_TBI          (0x06)
 #define RGMII_FER_GMII         (0x07)
+#define RGMII_FER_MII          (RGMII_FER_GMII)
 
 #define RGMII_FER_V(__x)       ((__x - 2) * 4)