drm/i915/dg2: Update steering tables

DG2's replicated register ranges are almost the same at XeHP SDV with
the exception of one LNCF sub-range that switches to gslice steering.
We can re-use the XeHP SDV mslice steering table and just provide a
DG2-specific LNCF steering table.

Bspec: 66534
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-5-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 93bfec4..62d40c9 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -103,6 +103,12 @@ static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = {
        {},
 };
 
+static const struct intel_mmio_range dg2_lncf_steering_table[] = {
+       { 0x00B000, 0x00B0FF },
+       { 0x00D880, 0x00D8FF },
+       {},
+};
+
 static u16 slicemask(struct intel_gt *gt, int count)
 {
        u64 dss_mask = intel_sseu_get_subslices(&gt->info.sseu, 0);
@@ -129,7 +135,10 @@ int intel_gt_init_mmio(struct intel_gt *gt)
                        (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
                         GEN12_MEML3_EN_MASK);
 
-       if (IS_XEHPSDV(i915)) {
+       if (IS_DG2(i915)) {
+               gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
+               gt->steering_table[LNCF] = dg2_lncf_steering_table;
+       } else if (IS_XEHPSDV(i915)) {
                gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
                gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
        } else if (GRAPHICS_VER(i915) >= 11 &&