dmaengine: dw-edma: Improve number of channels check
authorGustavo Pimentel <Gustavo.Pimentel@synopsys.com>
Thu, 18 Feb 2021 19:04:01 +0000 (20:04 +0100)
committerVinod Koul <vkoul@kernel.org>
Tue, 16 Mar 2021 17:28:53 +0000 (22:58 +0530)
It was added some extra checks to ensure that the driver doesn't try to
use more DMA channels than actually are available in hardware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Link: https://lore.kernel.org/r/cfb2b0a4f97ae9dc83ebe5ea59d6a51d69ea3654.1613674948.git.gustavo.pimentel@synopsys.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/dma/dw-edma/dw-edma-core.c
drivers/dma/dw-edma/dw-edma-core.h

index 1227a3e..cc39107 100644 (file)
@@ -914,19 +914,16 @@ int dw_edma_probe(struct dw_edma_chip *chip)
 
        raw_spin_lock_init(&dw->lock);
 
-       if (!dw->wr_ch_cnt) {
-               /* Find out how many write channels are supported by hardware */
-               dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE);
-               if (!dw->wr_ch_cnt)
-                       return -EINVAL;
-       }
+       dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt,
+                             dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE));
+       dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH);
 
-       if (!dw->rd_ch_cnt) {
-               /* Find out how many read channels are supported by hardware */
-               dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ);
-               if (!dw->rd_ch_cnt)
-                       return -EINVAL;
-       }
+       dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt,
+                             dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ));
+       dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH);
+
+       if (!dw->wr_ch_cnt && !dw->rd_ch_cnt)
+               return -EINVAL;
 
        dev_vdbg(dev, "Channels:\twrite=%d, read=%d\n",
                 dw->wr_ch_cnt, dw->rd_ch_cnt);
index f72ebaa..650b1c7 100644 (file)
@@ -15,6 +15,8 @@
 #include "../virt-dma.h"
 
 #define EDMA_LL_SZ                                     24
+#define EDMA_MAX_WR_CH                                 8
+#define EDMA_MAX_RD_CH                                 8
 
 enum dw_edma_dir {
        EDMA_DIR_WRITE = 0,