ARM: dts: rmobile: Import R8A7790 DTS from Linux 4.15-rc8
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Sun, 7 Jan 2018 19:17:23 +0000 (20:17 +0100)
committerMarek Vasut <marex@denx.de>
Sat, 27 Jan 2018 19:38:53 +0000 (20:38 +0100)
Import the Renesas R8A7790 DTS and headers from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
arch/arm/dts/r8a7790-lager.dts [new file with mode: 0644]
arch/arm/dts/r8a7790.dtsi [new file with mode: 0644]
include/dt-bindings/clock/r8a7790-clock.h [new file with mode: 0644]
include/dt-bindings/clock/r8a7790-cpg-mssr.h [new file with mode: 0644]
include/dt-bindings/power/r8a7790-sysc.h [new file with mode: 0644]

diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts
new file mode 100644 (file)
index 0000000..0230b42
--- /dev/null
@@ -0,0 +1,856 @@
+/*
+ * Device Tree Source for the Lager board
+ *
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
+ * Copyright (C) 2015-2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/*
+ * SSI-AK4643
+ *
+ * SW1: 1: AK4643
+ *      2: CN22
+ *      3: ADV7511
+ *
+ * This command is required when Playback/Capture
+ *
+ *     amixer set "LINEOUT Mixer DACL" on
+ *     amixer set "DVC Out" 100%
+ *     amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ *     amixer set "DVC Out Mute" on
+ *     amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *     amixer set "DVC Out Ramp" on
+ *     aplay xxx.wav &
+ *     amixer set "DVC Out"  80%  // Volume Down
+ *     amixer set "DVC Out" 100%  // Volume Up
+ */
+
+/dts-v1/;
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+       model = "Lager";
+       compatible = "renesas,lager", "renesas,r8a7790";
+
+       aliases {
+               serial0 = &scif0;
+               serial1 = &scifa1;
+               i2c8 = &gpioi2c1;
+               i2c10 = &i2cexio0;
+               i2c11 = &i2cexio1;
+       };
+
+       chosen {
+               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       memory@140000000 {
+               device_type = "memory";
+               reg = <1 0x40000000 0 0xc0000000>;
+       };
+
+       lbsc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+
+       keyboard {
+               compatible = "gpio-keys";
+
+               one {
+                       linux,code = <KEY_1>;
+                       label = "SW2-1";
+                       wakeup-source;
+                       debounce-interval = <20>;
+                       gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+               };
+               two {
+                       linux,code = <KEY_2>;
+                       label = "SW2-2";
+                       wakeup-source;
+                       debounce-interval = <20>;
+                       gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+               };
+               three {
+                       linux,code = <KEY_3>;
+                       label = "SW2-3";
+                       wakeup-source;
+                       debounce-interval = <20>;
+                       gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+               };
+               four {
+                       linux,code = <KEY_4>;
+                       label = "SW2-4";
+                       wakeup-source;
+                       debounce-interval = <20>;
+                       gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               led6 {
+                       gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+               };
+               led7 {
+                       gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
+               };
+               led8 {
+                       gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+               };
+       };
+
+       fixedregulator3v3: regulator-3v3 {
+               compatible = "regulator-fixed";
+               regulator-name = "fixed-3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+
+       vcc_sdhi0: regulator-vcc-sdhi0 {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDHI0 Vcc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vccq_sdhi0: regulator-vccq-sdhi0 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI0 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1
+                         1800000 0>;
+       };
+
+       vcc_sdhi2: regulator-vcc-sdhi2 {
+               compatible = "regulator-fixed";
+
+               regulator-name = "SDHI2 Vcc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       vccq_sdhi2: regulator-vccq-sdhi2 {
+               compatible = "regulator-gpio";
+
+               regulator-name = "SDHI2 VccQ";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+
+               gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
+               gpios-states = <1>;
+               states = <3300000 1
+                         1800000 0>;
+       };
+
+       audio_clock: audio_clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <11289600>;
+       };
+
+       rsnd_ak4643: sound {
+               compatible = "simple-audio-card";
+
+               simple-audio-card,format = "left_j";
+               simple-audio-card,bitclock-master = <&sndcodec>;
+               simple-audio-card,frame-master = <&sndcodec>;
+
+               sndcpu: simple-audio-card,cpu {
+                       sound-dai = <&rcar_sound>;
+               };
+
+               sndcodec: simple-audio-card,codec {
+                       sound-dai = <&ak4643>;
+                       clocks = <&audio_clock>;
+               };
+       };
+
+       vga-encoder {
+               compatible = "adi,adv7123";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7123_in: endpoint {
+                                       remote-endpoint = <&du_out_rgb>;
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               adv7123_out: endpoint {
+                                       remote-endpoint = <&vga_in>;
+                               };
+                       };
+               };
+       };
+
+       vga {
+               compatible = "vga-connector";
+
+               port {
+                       vga_in: endpoint {
+                               remote-endpoint = <&adv7123_out>;
+                       };
+               };
+       };
+
+       hdmi-in {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_in: endpoint {
+                               remote-endpoint = <&adv7612_in>;
+                       };
+               };
+       };
+
+       hdmi-out {
+               compatible = "hdmi-connector";
+               type = "a";
+
+               port {
+                       hdmi_con_out: endpoint {
+                               remote-endpoint = <&adv7511_out>;
+                       };
+               };
+       };
+
+       x2_clk: x2-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <148500000>;
+       };
+
+       x13_clk: x13-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <148500000>;
+       };
+
+       gpioi2c1: i2c-8 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "i2c-gpio";
+               status = "disabled";
+               gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
+                        &gpio1 16 GPIO_ACTIVE_HIGH /* scl */
+                       >;
+               i2c-gpio,delay-us = <5>;
+       };
+
+       /*
+        * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
+        * We use the I2C demuxer, so the desired IP core can be selected at runtime
+        * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
+        * Note: For testing the I2C slave feature, it is convenient to connect this
+        * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
+        * instantiate the slave device at runtime according to the documentation.
+        * You can then communicate with the slave via IIC3.
+        *
+        * IIC0/I2C0 does not appear to support fallback to GPIO.
+        */
+       i2cexio0: i2c-10 {
+               compatible = "i2c-demux-pinctrl";
+               i2c-parent = <&iic0>, <&i2c0>;
+               i2c-bus-name = "i2c-exio0";
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       /*
+        * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
+        * This is similar to the arangement described for i2cexio0 (above)
+        * with a fallback to GPIO also provided.
+        */
+       i2cexio1: i2c-11 {
+               compatible = "i2c-demux-pinctrl";
+               i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
+               i2c-bus-name = "i2c-exio1";
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+};
+
+&du {
+       pinctrl-0 = <&du_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
+                <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+                <&x13_clk>, <&x2_clk>;
+       clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
+                     "dclkin.0", "dclkin.1";
+
+       ports {
+               port@0 {
+                       endpoint {
+                               remote-endpoint = <&adv7123_in>;
+                       };
+               };
+               port@1 {
+                       endpoint {
+                               remote-endpoint = <&adv7511_in>;
+                       };
+               };
+               port@2 {
+                       lvds_connector: endpoint {
+                       };
+               };
+       };
+};
+
+&extal_clk {
+       clock-frequency = <20000000>;
+};
+
+&pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
+       du_pins: du {
+               groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
+               function = "du";
+       };
+
+       scif0_pins: scif0 {
+               groups = "scif0_data";
+               function = "scif0";
+       };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk";
+               function = "scif_clk";
+       };
+
+       ether_pins: ether {
+               groups = "eth_link", "eth_mdio", "eth_rmii";
+               function = "eth";
+       };
+
+       phy1_pins: phy1 {
+               groups = "intc_irq0";
+               function = "intc";
+       };
+
+       scifa1_pins: scifa1 {
+               groups = "scifa1_data";
+               function = "scifa1";
+       };
+
+       sdhi0_pins: sd0 {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <3300>;
+       };
+
+       sdhi0_pins_uhs: sd0_uhs {
+               groups = "sdhi0_data4", "sdhi0_ctrl";
+               function = "sdhi0";
+               power-source = <1800>;
+       };
+
+       sdhi2_pins: sd2 {
+               groups = "sdhi2_data4", "sdhi2_ctrl";
+               function = "sdhi2";
+               power-source = <3300>;
+       };
+
+       sdhi2_pins_uhs: sd2_uhs {
+               groups = "sdhi2_data4", "sdhi2_ctrl";
+               function = "sdhi2";
+               power-source = <1800>;
+       };
+
+       mmc1_pins: mmc1 {
+               groups = "mmc1_data8", "mmc1_ctrl";
+               function = "mmc1";
+       };
+
+       qspi_pins: qspi {
+               groups = "qspi_ctrl", "qspi_data4";
+               function = "qspi";
+       };
+
+       msiof1_pins: msiof1 {
+               groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
+                                "msiof1_tx";
+               function = "msiof1";
+       };
+
+       i2c0_pins: i2c0 {
+               groups = "i2c0";
+               function = "i2c0";
+       };
+
+       iic0_pins: iic0 {
+               groups = "iic0";
+               function = "iic0";
+       };
+
+       i2c1_pins: i2c1 {
+               groups = "i2c1";
+               function = "i2c1";
+       };
+
+       iic1_pins: iic1 {
+               groups = "iic1";
+               function = "iic1";
+       };
+
+       iic2_pins: iic2 {
+               groups = "iic2";
+               function = "iic2";
+       };
+
+       iic3_pins: iic3 {
+               groups = "iic3";
+               function = "iic3";
+       };
+
+       hsusb_pins: hsusb {
+               groups = "usb0_ovc_vbus";
+               function = "usb0";
+       };
+
+       usb0_pins: usb0 {
+               groups = "usb0";
+               function = "usb0";
+       };
+
+       usb1_pins: usb1 {
+               groups = "usb1";
+               function = "usb1";
+       };
+
+       usb2_pins: usb2 {
+               groups = "usb2";
+               function = "usb2";
+       };
+
+       vin0_pins: vin0 {
+               groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
+               function = "vin0";
+       };
+
+       vin1_pins: vin1 {
+               groups = "vin1_data8", "vin1_clk";
+               function = "vin1";
+       };
+
+       sound_pins: sound {
+               groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
+               function = "ssi";
+       };
+
+       sound_clk_pins: sound_clk {
+               groups = "audio_clk_a";
+               function = "audio_clk";
+       };
+};
+
+&ether {
+       pinctrl-0 = <&ether_pins &phy1_pins>;
+       pinctrl-names = "default";
+
+       phy-handle = <&phy1>;
+       renesas,ether-link-active-low;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               micrel,led-mode = <1>;
+       };
+};
+
+&cmt0 {
+       status = "okay";
+};
+
+&mmcif1 {
+       pinctrl-0 = <&mmc1_pins>;
+       pinctrl-names = "default";
+
+       vmmc-supply = <&fixedregulator3v3>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&sata1 {
+       status = "okay";
+};
+
+&qspi {
+       pinctrl-0 = <&qspi_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       flash: flash@0 {
+               compatible = "spansion,s25fl512s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <30000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+               spi-cpha;
+               spi-cpol;
+               m25p,fast-read;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "loader";
+                               reg = <0x00000000 0x00040000>;
+                               read-only;
+                       };
+                       partition@40000 {
+                               label = "user";
+                               reg = <0x00040000 0x00400000>;
+                               read-only;
+                       };
+                       partition@440000 {
+                               label = "flash";
+                               reg = <0x00440000 0x03bc0000>;
+                       };
+               };
+       };
+};
+
+&scif0 {
+       pinctrl-0 = <&scif0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&scifa1 {
+       pinctrl-0 = <&scifa1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&scif_clk {
+       clock-frequency = <14745600>;
+};
+
+&msiof1 {
+       pinctrl-0 = <&msiof1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       pmic: pmic@0 {
+               compatible = "renesas,r2a11302ft";
+               reg = <0>;
+               spi-max-frequency = <6000000>;
+               spi-cpol;
+               spi-cpha;
+       };
+};
+
+&sdhi0 {
+       pinctrl-0 = <&sdhi0_pins>;
+       pinctrl-1 = <&sdhi0_pins_uhs>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&vcc_sdhi0>;
+       vqmmc-supply = <&vccq_sdhi0>;
+       cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+       status = "okay";
+};
+
+&sdhi2 {
+       pinctrl-0 = <&sdhi2_pins>;
+       pinctrl-1 = <&sdhi2_pins_uhs>;
+       pinctrl-names = "default", "state_uhs";
+
+       vmmc-supply = <&vcc_sdhi2>;
+       vqmmc-supply = <&vccq_sdhi2>;
+       cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+       sd-uhs-sdr50;
+       status = "okay";
+};
+
+&cpu0 {
+       cpu0-supply = <&vdd_dvfs>;
+};
+
+&i2c0  {
+       pinctrl-0 = <&i2c0_pins>;
+       pinctrl-names = "i2c-exio0";
+};
+
+&iic0  {
+       pinctrl-0 = <&iic0_pins>;
+       pinctrl-names = "i2c-exio0";
+};
+
+&i2c1  {
+       pinctrl-0 = <&i2c1_pins>;
+       pinctrl-names = "i2c-exio1";
+};
+
+&iic1  {
+       pinctrl-0 = <&iic1_pins>;
+       pinctrl-names = "i2c-exio1";
+};
+
+&iic2  {
+       status = "okay";
+       pinctrl-0 = <&iic2_pins>;
+       pinctrl-names = "default";
+
+       clock-frequency = <100000>;
+
+       ak4643: codec@12 {
+               compatible = "asahi-kasei,ak4643";
+               #sound-dai-cells = <0>;
+               reg = <0x12>;
+       };
+
+       composite-in@20 {
+               compatible = "adi,adv7180";
+               reg = <0x20>;
+               remote = <&vin1>;
+
+               port {
+                       adv7180: endpoint {
+                               bus-width = <8>;
+                               remote-endpoint = <&vin1ep0>;
+                       };
+               };
+       };
+
+       hdmi@39 {
+               compatible = "adi,adv7511w";
+               reg = <0x39>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+               adi,input-depth = <8>;
+               adi,input-colorspace = "rgb";
+               adi,input-clock = "1x";
+               adi,input-style = <1>;
+               adi,input-justification = "evenly";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7511_in: endpoint {
+                                       remote-endpoint = <&du_out_lvds0>;
+                               };
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                               adv7511_out: endpoint {
+                                       remote-endpoint = <&hdmi_con_out>;
+                               };
+                       };
+               };
+       };
+
+       hdmi-in@4c {
+               compatible = "adi,adv7612";
+               reg = <0x4c>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+               default-input = <0>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               adv7612_in: endpoint {
+                                       remote-endpoint = <&hdmi_con_in>;
+                               };
+                       };
+
+                       port@2 {
+                               reg = <2>;
+                               adv7612_out: endpoint {
+                                       remote-endpoint = <&vin0ep2>;
+                               };
+                       };
+               };
+       };
+};
+
+&iic3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&iic3_pins>;
+       status = "okay";
+
+       pmic@58 {
+               compatible = "dlg,da9063";
+               reg = <0x58>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-controller;
+
+               rtc {
+                       compatible = "dlg,da9063-rtc";
+               };
+
+               wdt {
+                       compatible = "dlg,da9063-watchdog";
+               };
+       };
+
+       vdd_dvfs: regulator@68 {
+               compatible = "dlg,da9210";
+               reg = <0x68>;
+               interrupt-parent = <&irqc0>;
+               interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+               regulator-min-microvolt = <1000000>;
+               regulator-max-microvolt = <1000000>;
+               regulator-boot-on;
+               regulator-always-on;
+       };
+};
+
+&pci0 {
+       status = "okay";
+       pinctrl-0 = <&usb0_pins>;
+       pinctrl-names = "default";
+};
+
+&pci1 {
+       status = "okay";
+       pinctrl-0 = <&usb1_pins>;
+       pinctrl-names = "default";
+};
+
+&xhci {
+       status = "okay";
+       pinctrl-0 = <&usb2_pins>;
+       pinctrl-names = "default";
+};
+
+&pci2 {
+       status = "okay";
+       pinctrl-0 = <&usb2_pins>;
+       pinctrl-names = "default";
+};
+
+&hsusb {
+       status = "okay";
+       pinctrl-0 = <&hsusb_pins>;
+       pinctrl-names = "default";
+       renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
+
+&usbphy {
+       status = "okay";
+};
+
+/* HDMI video input */
+&vin0 {
+       pinctrl-0 = <&vin0_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       port {
+               vin0ep2: endpoint {
+                       remote-endpoint = <&adv7612_out>;
+                       bus-width = <24>;
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+                       pclk-sample = <1>;
+                       data-active = <1>;
+               };
+       };
+};
+
+/* composite video input */
+&vin1 {
+       pinctrl-0 = <&vin1_pins>;
+       pinctrl-names = "default";
+
+       status = "okay";
+
+       port {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vin1ep0: endpoint {
+                       remote-endpoint = <&adv7180>;
+                       bus-width = <8>;
+               };
+       };
+};
+
+&rcar_sound {
+       pinctrl-0 = <&sound_pins &sound_clk_pins>;
+       pinctrl-names = "default";
+
+       /* Single DAI */
+       #sound-dai-cells = <0>;
+
+       status = "okay";
+
+       rcar_sound,dai {
+               dai0 {
+                       playback = <&ssi0 &src2 &dvc0>;
+                       capture  = <&ssi1 &src3 &dvc1>;
+               };
+       };
+};
+
+&ssi1 {
+       shared-pin;
+};
diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
new file mode 100644 (file)
index 0000000..9678487
--- /dev/null
@@ -0,0 +1,1665 @@
+/*
+ * Device Tree Source for the r8a7790 SoC
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7790-sysc.h>
+
+/ {
+       compatible = "renesas,r8a7790";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &iic0;
+               i2c5 = &iic1;
+               i2c6 = &iic2;
+               i2c7 = &iic3;
+               spi0 = &qspi;
+               spi1 = &msiof0;
+               spi2 = &msiof1;
+               spi3 = &msiof2;
+               spi4 = &msiof3;
+               vin0 = &vin0;
+               vin1 = &vin1;
+               vin2 = &vin2;
+               vin3 = &vin3;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "renesas,apmu";
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0>;
+                       clock-frequency = <1300000000>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+                       clock-latency = <300000>; /* 300 us */
+                       power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+                       next-level-cache = <&L2_CA15>;
+                       capacity-dmips-mhz = <1024>;
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+                       clock-frequency = <1300000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+                       power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+                       next-level-cache = <&L2_CA15>;
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <2>;
+                       clock-frequency = <1300000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+                       power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+                       next-level-cache = <&L2_CA15>;
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <3>;
+                       clock-frequency = <1300000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
+                       power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+                       next-level-cache = <&L2_CA15>;
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu4: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x100>;
+                       clock-frequency = <780000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+                       power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+                       next-level-cache = <&L2_CA7>;
+                       capacity-dmips-mhz = <539>;
+               };
+
+               cpu5: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x101>;
+                       clock-frequency = <780000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+                       power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+                       next-level-cache = <&L2_CA7>;
+                       capacity-dmips-mhz = <539>;
+               };
+
+               cpu6: cpu@102 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x102>;
+                       clock-frequency = <780000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+                       power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+                       next-level-cache = <&L2_CA7>;
+                       capacity-dmips-mhz = <539>;
+               };
+
+               cpu7: cpu@103 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x103>;
+                       clock-frequency = <780000000>;
+                       clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
+                       power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+                       next-level-cache = <&L2_CA7>;
+                       capacity-dmips-mhz = <539>;
+               };
+
+               L2_CA15: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A7790_PD_CA15_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+
+               L2_CA7: cache-controller-1 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A7790_PD_CA7_SCU>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+       };
+
+       thermal-zones {
+               cpu_thermal: cpu-thermal {
+                       polling-delay-passive   = <0>;
+                       polling-delay           = <0>;
+
+                       thermal-sensors = <&thermal>;
+
+                       trips {
+                               cpu-crit {
+                                       temperature     = <115000>;
+                                       hysteresis      = <0>;
+                                       type            = "critical";
+                               };
+                       };
+                       cooling-maps {
+                       };
+               };
+       };
+
+       apmu@e6151000 {
+               compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+               reg = <0 0xe6151000 0 0x188>;
+               cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+       };
+
+       apmu@e6152000 {
+               compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+               reg = <0 0xe6152000 0 0x188>;
+               cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+       };
+
+       gic: interrupt-controller@f1001000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0 0xf1001000 0 0x1000>,
+                       <0 0xf1002000 0 0x2000>,
+                       <0 0xf1004000 0 0x2000>,
+                       <0 0xf1006000 0 0x2000>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               clocks = <&cpg CPG_MOD 408>;
+               clock-names = "clk";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 408>;
+       };
+
+       gpio0: gpio@e6050000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6050000 0 0x50>;
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 0 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 912>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 912>;
+       };
+
+       gpio1: gpio@e6051000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6051000 0 0x50>;
+               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 32 30>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 911>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 911>;
+       };
+
+       gpio2: gpio@e6052000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6052000 0 0x50>;
+               interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 64 30>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 910>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 910>;
+       };
+
+       gpio3: gpio@e6053000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6053000 0 0x50>;
+               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 96 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 909>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 909>;
+       };
+
+       gpio4: gpio@e6054000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6054000 0 0x50>;
+               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 128 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 908>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 908>;
+       };
+
+       gpio5: gpio@e6055000 {
+               compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
+               reg = <0 0xe6055000 0 0x50>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               gpio-ranges = <&pfc 0 160 32>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               clocks = <&cpg CPG_MOD 907>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 907>;
+       };
+
+       thermal: thermal@e61f0000 {
+               compatible =    "renesas,thermal-r8a7790",
+                               "renesas,rcar-gen2-thermal",
+                               "renesas,rcar-thermal";
+               reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+               interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 522>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 522>;
+               #thermal-sensor-cells = <0>;
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       cmt0: timer@ffca0000 {
+               compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+               reg = <0 0xffca0000 0 0x1004>;
+               interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 124>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 124>;
+
+               renesas,channels-mask = <0x60>;
+
+               status = "disabled";
+       };
+
+       cmt1: timer@e6130000 {
+               compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+               reg = <0 0xe6130000 0 0x1004>;
+               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 329>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 329>;
+
+               renesas,channels-mask = <0xff>;
+
+               status = "disabled";
+       };
+
+       irqc0: interrupt-controller@e61c0000 {
+               compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               reg = <0 0xe61c0000 0 0x200>;
+               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 407>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 407>;
+       };
+
+       dmac0: dma-controller@e6700000 {
+               compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+               reg = <0 0xe6700000 0 0x20000>;
+               interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12", "ch13", "ch14";
+               clocks = <&cpg CPG_MOD 219>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 219>;
+               #dma-cells = <1>;
+               dma-channels = <15>;
+       };
+
+       dmac1: dma-controller@e6720000 {
+               compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+               reg = <0 0xe6720000 0 0x20000>;
+               interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12", "ch13", "ch14";
+               clocks = <&cpg CPG_MOD 218>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 218>;
+               #dma-cells = <1>;
+               dma-channels = <15>;
+       };
+
+       audma0: dma-controller@ec700000 {
+               compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+               reg = <0 0xec700000 0 0x10000>;
+               interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12";
+               clocks = <&cpg CPG_MOD 502>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 502>;
+               #dma-cells = <1>;
+               dma-channels = <13>;
+       };
+
+       audma1: dma-controller@ec720000 {
+               compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
+               reg = <0 0xec720000 0 0x10000>;
+               interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "error",
+                               "ch0", "ch1", "ch2", "ch3",
+                               "ch4", "ch5", "ch6", "ch7",
+                               "ch8", "ch9", "ch10", "ch11",
+                               "ch12";
+               clocks = <&cpg CPG_MOD 501>;
+               clock-names = "fck";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 501>;
+               #dma-cells = <1>;
+               dma-channels = <13>;
+       };
+
+       usb_dmac0: dma-controller@e65a0000 {
+               compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+               reg = <0 0xe65a0000 0 0x100>;
+               interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "ch0", "ch1";
+               clocks = <&cpg CPG_MOD 330>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 330>;
+               #dma-cells = <1>;
+               dma-channels = <2>;
+       };
+
+       usb_dmac1: dma-controller@e65b0000 {
+               compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
+               reg = <0 0xe65b0000 0 0x100>;
+               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "ch0", "ch1";
+               clocks = <&cpg CPG_MOD 331>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 331>;
+               #dma-cells = <1>;
+               dma-channels = <2>;
+       };
+
+       i2c0: i2c@e6508000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6508000 0 0x40>;
+               interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 931>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 931>;
+               i2c-scl-internal-delay-ns = <110>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@e6518000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6518000 0 0x40>;
+               interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 930>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 930>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@e6530000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6530000 0 0x40>;
+               interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 929>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 929>;
+               i2c-scl-internal-delay-ns = <6>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@e6540000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
+               reg = <0 0xe6540000 0 0x40>;
+               interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 928>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 928>;
+               i2c-scl-internal-delay-ns = <110>;
+               status = "disabled";
+       };
+
+       iic0: i2c@e6500000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe6500000 0 0x425>;
+               interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 318>;
+               dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                      <&dmac1 0x61>, <&dmac1 0x62>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 318>;
+               status = "disabled";
+       };
+
+       iic1: i2c@e6510000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe6510000 0 0x425>;
+               interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 323>;
+               dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                      <&dmac1 0x65>, <&dmac1 0x66>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 323>;
+               status = "disabled";
+       };
+
+       iic2: i2c@e6520000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe6520000 0 0x425>;
+               interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 300>;
+               dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+                      <&dmac1 0x69>, <&dmac1 0x6a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 300>;
+               status = "disabled";
+       };
+
+       iic3: i2c@e60b0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+                            "renesas,rmobile-iic";
+               reg = <0 0xe60b0000 0 0x425>;
+               interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 926>;
+               dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                      <&dmac1 0x77>, <&dmac1 0x78>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 926>;
+               status = "disabled";
+       };
+
+       mmcif0: mmc@ee200000 {
+               compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+               reg = <0 0xee200000 0 0x80>;
+               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 315>;
+               dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                      <&dmac1 0xd1>, <&dmac1 0xd2>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 315>;
+               reg-io-width = <4>;
+               status = "disabled";
+               max-frequency = <97500000>;
+       };
+
+       mmcif1: mmc@ee220000 {
+               compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+               reg = <0 0xee220000 0 0x80>;
+               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 305>;
+               dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+                      <&dmac1 0xe1>, <&dmac1 0xe2>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 305>;
+               reg-io-width = <4>;
+               status = "disabled";
+               max-frequency = <97500000>;
+       };
+
+       pfc: pin-controller@e6060000 {
+               compatible = "renesas,pfc-r8a7790";
+               reg = <0 0xe6060000 0 0x250>;
+       };
+
+       sdhi0: sd@ee100000 {
+               compatible = "renesas,sdhi-r8a7790";
+               reg = <0 0xee100000 0 0x328>;
+               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 314>;
+               dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                      <&dmac1 0xcd>, <&dmac1 0xce>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <195000000>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 314>;
+               status = "disabled";
+       };
+
+       sdhi1: sd@ee120000 {
+               compatible = "renesas,sdhi-r8a7790";
+               reg = <0 0xee120000 0 0x328>;
+               interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 313>;
+               dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+                      <&dmac1 0xc9>, <&dmac1 0xca>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <195000000>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 313>;
+               status = "disabled";
+       };
+
+       sdhi2: sd@ee140000 {
+               compatible = "renesas,sdhi-r8a7790";
+               reg = <0 0xee140000 0 0x100>;
+               interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 312>;
+               dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                      <&dmac1 0xc1>, <&dmac1 0xc2>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <97500000>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 312>;
+               status = "disabled";
+       };
+
+       sdhi3: sd@ee160000 {
+               compatible = "renesas,sdhi-r8a7790";
+               reg = <0 0xee160000 0 0x100>;
+               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 311>;
+               dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                      <&dmac1 0xd3>, <&dmac1 0xd4>;
+               dma-names = "tx", "rx", "tx", "rx";
+               max-frequency = <97500000>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 311>;
+               status = "disabled";
+       };
+
+       scifa0: serial@e6c40000 {
+               compatible = "renesas,scifa-r8a7790",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c40000 0 64>;
+               interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 204>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                      <&dmac1 0x21>, <&dmac1 0x22>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 204>;
+               status = "disabled";
+       };
+
+       scifa1: serial@e6c50000 {
+               compatible = "renesas,scifa-r8a7790",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c50000 0 64>;
+               interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 203>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                      <&dmac1 0x25>, <&dmac1 0x26>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 203>;
+               status = "disabled";
+       };
+
+       scifa2: serial@e6c60000 {
+               compatible = "renesas,scifa-r8a7790",
+                            "renesas,rcar-gen2-scifa", "renesas,scifa";
+               reg = <0 0xe6c60000 0 64>;
+               interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 202>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                      <&dmac1 0x27>, <&dmac1 0x28>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 202>;
+               status = "disabled";
+       };
+
+       scifb0: serial@e6c20000 {
+               compatible = "renesas,scifb-r8a7790",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6c20000 0 0x100>;
+               interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 206>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                      <&dmac1 0x3d>, <&dmac1 0x3e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 206>;
+               status = "disabled";
+       };
+
+       scifb1: serial@e6c30000 {
+               compatible = "renesas,scifb-r8a7790",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6c30000 0 0x100>;
+               interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 207>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                      <&dmac1 0x19>, <&dmac1 0x1a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 207>;
+               status = "disabled";
+       };
+
+       scifb2: serial@e6ce0000 {
+               compatible = "renesas,scifb-r8a7790",
+                            "renesas,rcar-gen2-scifb", "renesas,scifb";
+               reg = <0 0xe6ce0000 0 0x100>;
+               interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 216>;
+               clock-names = "fck";
+               dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                      <&dmac1 0x1d>, <&dmac1 0x1e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 216>;
+               status = "disabled";
+       };
+
+       scif0: serial@e6e60000 {
+               compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e60000 0 64>;
+               interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                      <&dmac1 0x29>, <&dmac1 0x2a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 721>;
+               status = "disabled";
+       };
+
+       scif1: serial@e6e68000 {
+               compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e68000 0 64>;
+               interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                      <&dmac1 0x2d>, <&dmac1 0x2e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 720>;
+               status = "disabled";
+       };
+
+       scif2: serial@e6e56000 {
+               compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
+                            "renesas,scif";
+               reg = <0 0xe6e56000 0 64>;
+               interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                      <&dmac1 0x2b>, <&dmac1 0x2c>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 310>;
+               status = "disabled";
+       };
+
+       hscif0: serial@e62c0000 {
+               compatible = "renesas,hscif-r8a7790",
+                            "renesas,rcar-gen2-hscif", "renesas,hscif";
+               reg = <0 0xe62c0000 0 96>;
+               interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                      <&dmac1 0x39>, <&dmac1 0x3a>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 717>;
+               status = "disabled";
+       };
+
+       hscif1: serial@e62c8000 {
+               compatible = "renesas,hscif-r8a7790",
+                            "renesas,rcar-gen2-hscif", "renesas,hscif";
+               reg = <0 0xe62c8000 0 96>;
+               interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                      <&dmac1 0x4d>, <&dmac1 0x4e>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 716>;
+               status = "disabled";
+       };
+
+       icram0: sram@e63a0000 {
+               compatible = "mmio-sram";
+               reg = <0 0xe63a0000 0 0x12000>;
+       };
+
+       icram1: sram@e63c0000 {
+               compatible = "mmio-sram";
+               reg = <0 0xe63c0000 0 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0xe63c0000 0x1000>;
+
+               smp-sram@0 {
+                       compatible = "renesas,smp-sram";
+                       reg = <0 0x10>;
+               };
+       };
+
+       ether: ethernet@ee700000 {
+               compatible = "renesas,ether-r8a7790";
+               reg = <0 0xee700000 0 0x400>;
+               interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 813>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 813>;
+               phy-mode = "rmii";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       avb: ethernet@e6800000 {
+               compatible = "renesas,etheravb-r8a7790",
+                            "renesas,etheravb-rcar-gen2";
+               reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 812>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 812>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       sata0: sata@ee300000 {
+               compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+               reg = <0 0xee300000 0 0x2000>;
+               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 815>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 815>;
+               status = "disabled";
+       };
+
+       sata1: sata@ee500000 {
+               compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
+               reg = <0 0xee500000 0 0x2000>;
+               interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 814>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 814>;
+               status = "disabled";
+       };
+
+       hsusb: usb@e6590000 {
+               compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
+               reg = <0 0xe6590000 0 0x100>;
+               interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 704>;
+               dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                      <&usb_dmac1 0>, <&usb_dmac1 1>;
+               dma-names = "ch0", "ch1", "ch2", "ch3";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 704>;
+               renesas,buswait = <4>;
+               phys = <&usb0 1>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       usbphy: usb-phy@e6590100 {
+               compatible = "renesas,usb-phy-r8a7790",
+                            "renesas,rcar-gen2-usb-phy";
+               reg = <0 0xe6590100 0 0x100>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&cpg CPG_MOD 704>;
+               clock-names = "usbhs";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 704>;
+               status = "disabled";
+
+               usb0: usb-channel@0 {
+                       reg = <0>;
+                       #phy-cells = <1>;
+               };
+               usb2: usb-channel@2 {
+                       reg = <2>;
+                       #phy-cells = <1>;
+               };
+       };
+
+       vin0: video@e6ef0000 {
+               compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef0000 0 0x1000>;
+               interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 811>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 811>;
+               status = "disabled";
+       };
+
+       vin1: video@e6ef1000 {
+               compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef1000 0 0x1000>;
+               interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 810>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 810>;
+               status = "disabled";
+       };
+
+       vin2: video@e6ef2000 {
+               compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef2000 0 0x1000>;
+               interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 809>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 809>;
+               status = "disabled";
+       };
+
+       vin3: video@e6ef3000 {
+               compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
+               reg = <0 0xe6ef3000 0 0x1000>;
+               interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 808>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 808>;
+               status = "disabled";
+       };
+
+       vsp@fe920000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe920000 0 0x8000>;
+               interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 130>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 130>;
+       };
+
+       vsp@fe928000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe928000 0 0x8000>;
+               interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 131>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 131>;
+       };
+
+       vsp@fe930000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe930000 0 0x8000>;
+               interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 128>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 128>;
+       };
+
+       vsp@fe938000 {
+               compatible = "renesas,vsp1";
+               reg = <0 0xfe938000 0 0x8000>;
+               interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 127>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 127>;
+       };
+
+       du: display@feb00000 {
+               compatible = "renesas,du-r8a7790";
+               reg = <0 0xfeb00000 0 0x70000>,
+                     <0 0xfeb90000 0 0x1c>,
+                     <0 0xfeb94000 0 0x1c>;
+               reg-names = "du", "lvds.0", "lvds.1";
+               interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+                        <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+                        <&cpg CPG_MOD 725>;
+               clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                               du_out_rgb: endpoint {
+                               };
+                       };
+                       port@1 {
+                               reg = <1>;
+                               du_out_lvds0: endpoint {
+                               };
+                       };
+                       port@2 {
+                               reg = <2>;
+                               du_out_lvds1: endpoint {
+                               };
+                       };
+               };
+       };
+
+       can0: can@e6e80000 {
+               compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+               reg = <0 0xe6e80000 0 0x1000>;
+               interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+                        <&can_clk>;
+               clock-names = "clkp1", "clkp2", "can_clk";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 916>;
+               status = "disabled";
+       };
+
+       can1: can@e6e88000 {
+               compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
+               reg = <0 0xe6e88000 0 0x1000>;
+               interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
+                        <&can_clk>;
+               clock-names = "clkp1", "clkp2", "can_clk";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 915>;
+               status = "disabled";
+       };
+
+       jpu: jpeg-codec@fe980000 {
+               compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
+               reg = <0 0xfe980000 0 0x10300>;
+               interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 106>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 106>;
+       };
+
+       /* External root clock */
+       extal_clk: extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /* External PCIe clock - can be overridden by the board */
+       pcie_bus_clk: pcie_bus {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       /*
+        * The external audio clocks are configured as 0 Hz fixed frequency
+        * clocks by default.
+        * Boards that provide audio clocks should override them.
+        */
+       audio_clk_a: audio_clk_a {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+       audio_clk_b: audio_clk_b {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+       audio_clk_c: audio_clk_c {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       /* External SCIF clock */
+       scif_clk: scif {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       /* External USB clock - can be overridden by the board */
+       usb_extal_clk: usb_extal {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <48000000>;
+       };
+
+       /* External CAN clock */
+       can_clk: can {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       cpg: clock-controller@e6150000 {
+               compatible = "renesas,r8a7790-cpg-mssr";
+               reg = <0 0xe6150000 0 0x1000>;
+               clocks = <&extal_clk>, <&usb_extal_clk>;
+               clock-names = "extal", "usb_extal";
+               #clock-cells = <2>;
+               #power-domain-cells = <0>;
+               #reset-cells = <1>;
+       };
+
+       prr: chipid@ff000044 {
+               compatible = "renesas,prr";
+               reg = <0 0xff000044 0 4>;
+       };
+
+       rst: reset-controller@e6160000 {
+               compatible = "renesas,r8a7790-rst";
+               reg = <0 0xe6160000 0 0x0100>;
+       };
+
+       sysc: system-controller@e6180000 {
+               compatible = "renesas,r8a7790-sysc";
+               reg = <0 0xe6180000 0 0x0200>;
+               #power-domain-cells = <1>;
+       };
+
+       qspi: spi@e6b10000 {
+               compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+               reg = <0 0xe6b10000 0 0x2c>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 917>;
+               dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                      <&dmac1 0x17>, <&dmac1 0x18>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 917>;
+               num-cs = <1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof0: spi@e6e20000 {
+               compatible = "renesas,msiof-r8a7790",
+                            "renesas,rcar-gen2-msiof";
+               reg = <0 0xe6e20000 0 0x0064>;
+               interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 0>;
+               dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                      <&dmac1 0x51>, <&dmac1 0x52>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof1: spi@e6e10000 {
+               compatible = "renesas,msiof-r8a7790",
+                            "renesas,rcar-gen2-msiof";
+               reg = <0 0xe6e10000 0 0x0064>;
+               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 208>;
+               dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                      <&dmac1 0x55>, <&dmac1 0x56>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 208>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof2: spi@e6e00000 {
+               compatible = "renesas,msiof-r8a7790",
+                            "renesas,rcar-gen2-msiof";
+               reg = <0 0xe6e00000 0 0x0064>;
+               interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 205>;
+               dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                      <&dmac1 0x41>, <&dmac1 0x42>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 205>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       msiof3: spi@e6c90000 {
+               compatible = "renesas,msiof-r8a7790",
+                            "renesas,rcar-gen2-msiof";
+               reg = <0 0xe6c90000 0 0x0064>;
+               interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 215>;
+               dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+                      <&dmac1 0x45>, <&dmac1 0x46>;
+               dma-names = "tx", "rx", "tx", "rx";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 215>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       xhci: usb@ee000000 {
+               compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
+               reg = <0 0xee000000 0 0xc00>;
+               interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 328>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 328>;
+               phys = <&usb2 1>;
+               phy-names = "usb";
+               status = "disabled";
+       };
+
+       pci0: pci@ee090000 {
+               compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+               device_type = "pci";
+               reg = <0 0xee090000 0 0xc00>,
+                     <0 0xee080000 0 0x1100>;
+               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 703>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 703>;
+               status = "disabled";
+
+               bus-range = <0 0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+               interrupt-map-mask = <0xff00 0 0 0x7>;
+               interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+               usb@1,0 {
+                       reg = <0x800 0 0 0 0>;
+                       phys = <&usb0 0>;
+                       phy-names = "usb";
+               };
+
+               usb@2,0 {
+                       reg = <0x1000 0 0 0 0>;
+                       phys = <&usb0 0>;
+                       phy-names = "usb";
+               };
+       };
+
+       pci1: pci@ee0b0000 {
+               compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+               device_type = "pci";
+               reg = <0 0xee0b0000 0 0xc00>,
+                     <0 0xee0a0000 0 0x1100>;
+               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 703>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 703>;
+               status = "disabled";
+
+               bus-range = <1 1>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+               interrupt-map-mask = <0xff00 0 0 0x7>;
+               interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       pci2: pci@ee0d0000 {
+               compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+               device_type = "pci";
+               clocks = <&cpg CPG_MOD 703>;
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 703>;
+               reg = <0 0xee0d0000 0 0xc00>,
+                     <0 0xee0c0000 0 0x1100>;
+               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+
+               bus-range = <2 2>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               #interrupt-cells = <1>;
+               ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+               interrupt-map-mask = <0xff00 0 0 0x7>;
+               interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+               usb@1,0 {
+                       reg = <0x20800 0 0 0 0>;
+                       phys = <&usb2 0>;
+                       phy-names = "usb";
+               };
+
+               usb@2,0 {
+                       reg = <0x21000 0 0 0 0>;
+                       phys = <&usb2 0>;
+                       phy-names = "usb";
+               };
+       };
+
+       pciec: pcie@fe000000 {
+               compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
+               reg = <0 0xfe000000 0 0x80000>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+               bus-range = <0x00 0xff>;
+               device_type = "pci";
+               ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+                         0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+                         0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+                         0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+               /* Map all possible DDR as inbound ranges */
+               dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+                             0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0 0 0 0>;
+               interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+               clock-names = "pcie", "pcie_bus";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 319>;
+               status = "disabled";
+       };
+
+       rcar_sound: sound@ec500000 {
+               /*
+                * #sound-dai-cells is required
+                *
+                * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                */
+               compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
+               reg =   <0 0xec500000 0 0x1000>, /* SCU */
+                       <0 0xec5a0000 0 0x100>,  /* ADG */
+                       <0 0xec540000 0 0x1000>, /* SSIU */
+                       <0 0xec541000 0 0x280>,  /* SSI */
+                       <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+               reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+               clocks = <&cpg CPG_MOD 1005>,
+                        <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                        <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                        <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                        <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                        <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                        <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                        <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                        <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                        <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                        <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                        <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                        <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                        <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                        <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                        <&cpg CPG_CORE R8A7790_CLK_M2>;
+               clock-names = "ssi-all",
+                               "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+                               "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
+                               "src.9", "src.8", "src.7", "src.6", "src.5",
+                               "src.4", "src.3", "src.2", "src.1", "src.0",
+                               "ctu.0", "ctu.1",
+                               "mix.0", "mix.1",
+                               "dvc.0", "dvc.1",
+                               "clk_a", "clk_b", "clk_c", "clk_i";
+               power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+               resets = <&cpg 1005>,
+                        <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
+                        <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
+                        <&cpg 1014>, <&cpg 1015>;
+               reset-names = "ssi-all",
+                             "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
+                             "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
+
+               status = "disabled";
+
+               rcar_sound,dvc {
+                       dvc0: dvc-0 {
+                               dmas = <&audma1 0xbc>;
+                               dma-names = "tx";
+                       };
+                       dvc1: dvc-1 {
+                               dmas = <&audma1 0xbe>;
+                               dma-names = "tx";
+                       };
+               };
+
+               rcar_sound,mix {
+                       mix0: mix-0 { };
+                       mix1: mix-1 { };
+               };
+
+               rcar_sound,ctu {
+                       ctu00: ctu-0 { };
+                       ctu01: ctu-1 { };
+                       ctu02: ctu-2 { };
+                       ctu03: ctu-3 { };
+                       ctu10: ctu-4 { };
+                       ctu11: ctu-5 { };
+                       ctu12: ctu-6 { };
+                       ctu13: ctu-7 { };
+               };
+
+               rcar_sound,src {
+                       src0: src-0 {
+                               interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                               dma-names = "rx", "tx";
+                       };
+                       src1: src-1 {
+                               interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                               dma-names = "rx", "tx";
+                       };
+                       src2: src-2 {
+                               interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                               dma-names = "rx", "tx";
+                       };
+                       src3: src-3 {
+                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                               dma-names = "rx", "tx";
+                       };
+                       src4: src-4 {
+                               interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                               dma-names = "rx", "tx";
+                       };
+                       src5: src-5 {
+                               interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                               dma-names = "rx", "tx";
+                       };
+                       src6: src-6 {
+                               interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                               dma-names = "rx", "tx";
+                       };
+                       src7: src-7 {
+                               interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                               dma-names = "rx", "tx";
+                       };
+                       src8: src-8 {
+                               interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                               dma-names = "rx", "tx";
+                       };
+                       src9: src-9 {
+                               interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x97>, <&audma1 0xba>;
+                               dma-names = "rx", "tx";
+                       };
+               };
+
+               rcar_sound,ssi {
+                       ssi0: ssi-0 {
+                               interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi1: ssi-1 {
+                                interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi2: ssi-2 {
+                               interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi3: ssi-3 {
+                               interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi4: ssi-4 {
+                               interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi5: ssi-5 {
+                               interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi6: ssi-6 {
+                               interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi7: ssi-7 {
+                               interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi8: ssi-8 {
+                               interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+                       ssi9: ssi-9 {
+                               interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                               dma-names = "rx", "tx", "rxu", "txu";
+                       };
+               };
+       };
+
+       ipmmu_sy0: mmu@e6280000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6280000 0 0x1000>;
+               interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_sy1: mmu@e6290000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6290000 0 0x1000>;
+               interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_ds: mmu@e6740000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xe6740000 0 0x1000>;
+               interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_mp: mmu@ec680000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xec680000 0 0x1000>;
+               interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_mx: mmu@fe951000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xfe951000 0 0x1000>;
+               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+
+       ipmmu_rt: mmu@ffc80000 {
+               compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
+               reg = <0 0xffc80000 0 0x1000>;
+               interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+               #iommu-cells = <1>;
+               status = "disabled";
+       };
+};
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644 (file)
index 0000000..20641fa
--- /dev/null
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN               0
+#define R8A7790_CLK_PLL0               1
+#define R8A7790_CLK_PLL1               2
+#define R8A7790_CLK_PLL3               3
+#define R8A7790_CLK_LB                 4
+#define R8A7790_CLK_QSPI               5
+#define R8A7790_CLK_SDH                        6
+#define R8A7790_CLK_SD0                        7
+#define R8A7790_CLK_SD1                        8
+#define R8A7790_CLK_Z                  9
+#define R8A7790_CLK_RCAN               10
+#define R8A7790_CLK_ADSP               11
+
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0             0
+
+/* MSTP1 */
+#define R8A7790_CLK_VCP1               0
+#define R8A7790_CLK_VCP0               1
+#define R8A7790_CLK_VPC1               2
+#define R8A7790_CLK_VPC0               3
+#define R8A7790_CLK_JPU                        6
+#define R8A7790_CLK_SSP1               9
+#define R8A7790_CLK_TMU1               11
+#define R8A7790_CLK_3DG                        12
+#define R8A7790_CLK_2DDMAC             15
+#define R8A7790_CLK_FDP1_2             17
+#define R8A7790_CLK_FDP1_1             18
+#define R8A7790_CLK_FDP1_0             19
+#define R8A7790_CLK_TMU3               21
+#define R8A7790_CLK_TMU2               22
+#define R8A7790_CLK_CMT0               24
+#define R8A7790_CLK_TMU0               25
+#define R8A7790_CLK_VSP1_DU1           27
+#define R8A7790_CLK_VSP1_DU0           28
+#define R8A7790_CLK_VSP1_R             30
+#define R8A7790_CLK_VSP1_S             31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2             2
+#define R8A7790_CLK_SCIFA1             3
+#define R8A7790_CLK_SCIFA0             4
+#define R8A7790_CLK_MSIOF2             5
+#define R8A7790_CLK_SCIFB0             6
+#define R8A7790_CLK_SCIFB1             7
+#define R8A7790_CLK_MSIOF1             8
+#define R8A7790_CLK_MSIOF3             15
+#define R8A7790_CLK_SCIFB2             16
+#define R8A7790_CLK_SYS_DMAC1          18
+#define R8A7790_CLK_SYS_DMAC0          19
+
+/* MSTP3 */
+#define R8A7790_CLK_IIC2               0
+#define R8A7790_CLK_TPU0               4
+#define R8A7790_CLK_MMCIF1             5
+#define R8A7790_CLK_SCIF2              10
+#define R8A7790_CLK_SDHI3              11
+#define R8A7790_CLK_SDHI2              12
+#define R8A7790_CLK_SDHI1              13
+#define R8A7790_CLK_SDHI0              14
+#define R8A7790_CLK_MMCIF0             15
+#define R8A7790_CLK_IIC0               18
+#define R8A7790_CLK_PCIEC              19
+#define R8A7790_CLK_IIC1               23
+#define R8A7790_CLK_SSUSB              28
+#define R8A7790_CLK_CMT1               29
+#define R8A7790_CLK_USBDMAC0           30
+#define R8A7790_CLK_USBDMAC1           31
+
+/* MSTP4 */
+#define R8A7790_CLK_IRQC               7
+#define R8A7790_CLK_INTC_SYS           8
+
+/* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1                1
+#define R8A7790_CLK_AUDIO_DMAC0                2
+#define R8A7790_CLK_ADSP_MOD           6
+#define R8A7790_CLK_THERMAL            22
+#define R8A7790_CLK_PWM                        23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI               3
+#define R8A7790_CLK_HSUSB              4
+#define R8A7790_CLK_HSCIF1             16
+#define R8A7790_CLK_HSCIF0             17
+#define R8A7790_CLK_SCIF1              20
+#define R8A7790_CLK_SCIF0              21
+#define R8A7790_CLK_DU2                        22
+#define R8A7790_CLK_DU1                        23
+#define R8A7790_CLK_DU0                        24
+#define R8A7790_CLK_LVDS1              25
+#define R8A7790_CLK_LVDS0              26
+
+/* MSTP8 */
+#define R8A7790_CLK_MLB                        2
+#define R8A7790_CLK_VIN3               8
+#define R8A7790_CLK_VIN2               9
+#define R8A7790_CLK_VIN1               10
+#define R8A7790_CLK_VIN0               11
+#define R8A7790_CLK_ETHERAVB           12
+#define R8A7790_CLK_ETHER              13
+#define R8A7790_CLK_SATA1              14
+#define R8A7790_CLK_SATA0              15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5              7
+#define R8A7790_CLK_GPIO4              8
+#define R8A7790_CLK_GPIO3              9
+#define R8A7790_CLK_GPIO2              10
+#define R8A7790_CLK_GPIO1              11
+#define R8A7790_CLK_GPIO0              12
+#define R8A7790_CLK_RCAN1              15
+#define R8A7790_CLK_RCAN0              16
+#define R8A7790_CLK_QSPI_MOD           17
+#define R8A7790_CLK_IICDVFS            26
+#define R8A7790_CLK_I2C3               28
+#define R8A7790_CLK_I2C2               29
+#define R8A7790_CLK_I2C1               30
+#define R8A7790_CLK_I2C0               31
+
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL            5
+#define R8A7790_CLK_SSI9               6
+#define R8A7790_CLK_SSI8               7
+#define R8A7790_CLK_SSI7               8
+#define R8A7790_CLK_SSI6               9
+#define R8A7790_CLK_SSI5               10
+#define R8A7790_CLK_SSI4               11
+#define R8A7790_CLK_SSI3               12
+#define R8A7790_CLK_SSI2               13
+#define R8A7790_CLK_SSI1               14
+#define R8A7790_CLK_SSI0               15
+#define R8A7790_CLK_SCU_ALL            17
+#define R8A7790_CLK_SCU_DVC1           18
+#define R8A7790_CLK_SCU_DVC0           19
+#define R8A7790_CLK_SCU_CTU1_MIX1      20
+#define R8A7790_CLK_SCU_CTU0_MIX0      21
+#define R8A7790_CLK_SCU_SRC9           22
+#define R8A7790_CLK_SCU_SRC8           23
+#define R8A7790_CLK_SCU_SRC7           24
+#define R8A7790_CLK_SCU_SRC6           25
+#define R8A7790_CLK_SCU_SRC5           26
+#define R8A7790_CLK_SCU_SRC4           27
+#define R8A7790_CLK_SCU_SRC3           28
+#define R8A7790_CLK_SCU_SRC2           29
+#define R8A7790_CLK_SCU_SRC1           30
+#define R8A7790_CLK_SCU_SRC0           31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644 (file)
index 0000000..1625b8b
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z                  0
+#define R8A7790_CLK_Z2                 1
+#define R8A7790_CLK_ZG                 2
+#define R8A7790_CLK_ZTR                        3
+#define R8A7790_CLK_ZTRD2              4
+#define R8A7790_CLK_ZT                 5
+#define R8A7790_CLK_ZX                 6
+#define R8A7790_CLK_ZS                 7
+#define R8A7790_CLK_HP                 8
+#define R8A7790_CLK_I                  9
+#define R8A7790_CLK_B                  10
+#define R8A7790_CLK_LB                 11
+#define R8A7790_CLK_P                  12
+#define R8A7790_CLK_CL                 13
+#define R8A7790_CLK_M2                 14
+#define R8A7790_CLK_ADSP               15
+#define R8A7790_CLK_IMP                        16
+#define R8A7790_CLK_ZB3                        17
+#define R8A7790_CLK_ZB3D2              18
+#define R8A7790_CLK_DDR                        19
+#define R8A7790_CLK_SDH                        20
+#define R8A7790_CLK_SD0                        21
+#define R8A7790_CLK_SD1                        22
+#define R8A7790_CLK_SD2                        23
+#define R8A7790_CLK_SD3                        24
+#define R8A7790_CLK_MMC0               25
+#define R8A7790_CLK_MMC1               26
+#define R8A7790_CLK_MP                 27
+#define R8A7790_CLK_SSP                        28
+#define R8A7790_CLK_SSPRS              29
+#define R8A7790_CLK_QSPI               30
+#define R8A7790_CLK_CP                 31
+#define R8A7790_CLK_RCAN               32
+#define R8A7790_CLK_R                  33
+#define R8A7790_CLK_OSC                        34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
new file mode 100644 (file)
index 0000000..6af4e99
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7790_PD_CA15_CPU0            0
+#define R8A7790_PD_CA15_CPU1            1
+#define R8A7790_PD_CA15_CPU2            2
+#define R8A7790_PD_CA15_CPU3            3
+#define R8A7790_PD_CA7_CPU0             5
+#define R8A7790_PD_CA7_CPU1             6
+#define R8A7790_PD_CA7_CPU2             7
+#define R8A7790_PD_CA7_CPU3             8
+#define R8A7790_PD_CA15_SCU            12
+#define R8A7790_PD_SH_4A               16
+#define R8A7790_PD_RGX                 20
+#define R8A7790_PD_CA7_SCU             21
+#define R8A7790_PD_IMP                 24
+
+/* Always-on power area */
+#define R8A7790_PD_ALWAYS_ON           32
+
+#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */