}
bool
-can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr)
+can_write_m0(const aco_ptr<Instruction>& instr)
{
if (instr->isSALU())
return true;
+ /* VALU can't write m0 on any GPU generations. */
if (instr->isVALU())
- return gfx_level >= GFX9;
+ return false;
switch (instr->opcode) {
case aco_opcode::p_parallelcopy:
case aco_opcode::p_extract:
case aco_opcode::p_insert:
+ /* These pseudo instructions are implemented with SALU when writing m0. */
return true;
- case aco_opcode::p_reload:
- return gfx_level >= GFX9;
default:
+ /* Assume that no other instructions can write m0. */
return false;
}
}
uint8_t get_gfx11_true16_mask(aco_opcode op);
bool can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra);
bool can_use_DPP(const aco_ptr<Instruction>& instr, bool pre_ra, bool dpp8);
-bool can_write_m0(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr);
+bool can_write_m0(const aco_ptr<Instruction>& instr);
/* updates "instr" and returns the old instruction (or NULL if no update was needed) */
aco_ptr<Instruction> convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr);
aco_ptr<Instruction> convert_to_DPP(aco_ptr<Instruction>& instr, bool dpp8);
}
if (ctx.assignments[temp.id()].m0) {
if (get_reg_specified(ctx, reg_file, temp.regClass(), instr, m0) &&
- can_write_m0(ctx.program->gfx_level, instr))
+ can_write_m0(instr))
return m0;
}